參數(shù)資料
型號: PCD5013
廠商: NXP Semiconductors N.V.
英文描述: FLEX roaming decoder II
中文描述: FleX創(chuàng)建漫游解碼器二
文件頁數(shù): 24/76頁
文件大?。?/td> 270K
代理商: PCD5013
1999 Apr 12
24
Philips Semiconductors
Product specification
FLEX
roaming decoder II
PCD5013
8.4.10
T
IMING
C
ONTROL
P
ACKET
(ID = 06H)
The timing control packet gives the host control of the
timing used when the PCD5013 is in asynchronous mode.
The packet ID for the timing control packet is 6.
AST:
A-word search time (Table 15). The value of these
bits sets the A-word search time for all asynchronous
A-word searches in units of 80 ms (e.g. value of 1 is 80 ms,
a value of 2 is 160 ms, etc.). If the value is 0, the PCD5013
defaults to the 1-minute (MOT = 1) or 4-minute (MOT = 0)
A-word search time controlled by the MOT bit in the
configuration packet. Value after reset = 0.
ABT:
asynchronous battery-save time (Table 15).
The value of these bits sets the battery save time (time
from the beginning of one automatic noise detect to the
beginning of the next automatic noise detect) in
asynchronous mode in units of 80 ms (e.g. value of 1 is
80 ms, a value of 2 is 160 ms, etc.) If the value is 0, the
battery save time is set to the default value of 1.5 seconds.
The minimum allowed ABT is 320 ms, therefore values of
1, 2, 3, and 4 are invalid. Value after reset = 0.
8.4.11
S
TATUS PACKET
(ID = 7FH)
The status packet contains various types of information
that the host may require and is sent to the host:
Whenever the PCD5013 is polled and has no other data
to send
On events for which the PCD5013 is configured to send
the status packet (Sections 8.4.4 and 8.4.7). In this
case, the PCD5013 prompts the host to read a status
packet for the following conditions:
– SMU bit in the status packet and the SME bit in the
configuration packet are set
– MT bit in the status packet and the MTE bit in the
configuration packet are set
– EOF bit in the status packet is set
– LBU bit in the status packet is set
– EA bit in the status packet is set
– BOE bit in the status packet is set.
FIV:
frame information valid (Table 16). This bit is set,
when a valid frame information word has been received
since becoming synchronous to the system and the
f and c fields contain valid values. If this bit is clear, no
valid frame information words have been received since
the PCD5013 became synchronous to the system.
This value changes from 0 to 1 at the end of block 0
(Fig.18) of the frame in which the first frame information
word was properly received. It is cleared when the
PCD5013 goes into asynchronous mode (see SM bit
below). This bit is initialized to 0 when the PCD5013 is
reset and when the PCD5013 is turned off by clearing the
ON bit in the control packet.
f:
current frame number (Table 16). This value is updated
every frame regardless of whether the PCD5013 needs to
decode the frame. This value changes to its proper value
for a frame at the end of block 0 of the frame. The value of
these bits is not guaranteed when FIV is 0.
c:
current system cycle number (Table 16). This value is
updated every frame regardless of whether the PCD5013
needs to decode the frame. This value changes to its
proper value for a frame at the end of block 0 of the frame.
The value of these bits is not guaranteed when FIV is 0.
SM:
synchronous mode (Table 16). This bit is set, when
the PCD5013 is synchronous to the system.
The PCD5013 sets this bit when the first synchronization
words are received. It clears this bit when the PCD5013
has not properly received both synchronization words in
any frame for 8, 16, or 32 minutes (depending on the
number of assigned frames and the system collapse). This
bit is initialized to 0 when the PCD5013 is reset and when
it is turned off by clearing the ON bit in the control packet.
Table 15
Timing Control Packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
2
1
0
0
0
0
0
1
0
0
0
0
0
f
2
0
f
1
0
f
0
0
AST
7
ABT
7
AST
6
ABT
6
AST
5
ABT
5
AST
4
ABT
4
AST
3
ABT
3
AST
2
ABT
2
AST
1
ABT
1
AST
0
ABT
0
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