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參數(shù)資料
| 型號： | PCD5013 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | FLEX roaming decoder II |
| 中文描述： | FleX創(chuàng)建漫游解碼器二 |
| 文件頁數(shù)： | 21/76頁 |
| 文件大小： | 270K |
| 代理商： | PCD5013 |
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1999 Apr 12
21
Philips Semiconductors
Product specification
FLEX
roaming decoder II
PCD5013
8.4.7
C
ONTROL PACKET
(ID = 02H)
The control packet defines a number of different control
bits for the PCD5013.
FF:
force frame 0 to 7 (Table 12). When set, each of these
bits forces the PCD5013 to decode one of the FLEX
frames 0 to 7 irrespective of the system collapse value (for
details of collapse values see Section 8.6.2). For example,
if the system collapse causes the PCD5013 to decode
frames 0, 32, 64 and 96, setting FF
2
causes the PCD5013
to also decode FLEX
frame 2. This may be used to
acquire transmitted time information or channel attributes
(e.g. Local ID). Value after reset = 0.
SPM:
single phase mode (Table 12). When this bit is set,
the PCD5013 decodes only one of the transmitted phases.
When this bit is clear, the PCD5013 decodes all
transmitted phases. This value is determined by the
CAPCODE (Section 8.6). A change to this bit while the
PCD5013 is on does not take effect until the next block 0
of a frame. Value after reset = 0.
PS:
phase select (Tables 11 and 12). When the SPM bit is
set, these bits define which phase the PCD5013 shall
decode. This value is determined by the CAPCODE
(Section 8.6). A change to these bits, while the PCD5013
is on, does not take effect until the next block 0 of a frame.
Value after reset = 0.
Table 11
Phase selection (by PS bits)
PS
1
PS
0
DECODED PHASE (BASED ON
FLEX
DATA RATE)
1600 bits/s 3200 bits/s 6400 bits/s
0
0
1
1
0
1
0
1
A
A
A
A
A
A
C
C
A
B
C
D
SBI:
send block information words (BIW) 2 to 4
(Table 12). When this bit is set, BIWs with time and date
information and BIWs received in error are sent to the host,
(Section 8.7.9). Value after reset = 0.
MTC:
minute timer clear (Table 12). Setting this bit causes
the 1-minute timer to restart from 0 (Section 8.4.8).
ON:
turn on decoder (Table 12). When this bit is set, the
PCD5013 decodes FLEX
signals. If this bit is cleared,
signal processing stops. However, to assure proper
operation, the PCD5013 requires that it be set into
asynchronous mode when turned off. To achieve that the
following sequence must be used:
1.
Send control packet with ON bit clear (decoder off)
2.
Send control packet with ON bit set (decoder on)
3.
Send control packet with ON bit clear (decoder off).
Timing between these steps is specified below and is
measured from the positive edge of the last clock of one
packet to the positive edge of the last clock of the next
packet.
The minimum time between steps 1 and 2 is the greater
of 2 ms or the programmed shut-down time.
The programmed shut-down time is the sum of all of the
times programmed in the used receiver shut-down
settings packets.
There is no maximum time between steps 1 and 2.
The minimum time between steps 2 and 3 is 2 ms.
The maximum time between steps 2 and 3 is the
programmed warm-up time minus 2 ms.
The programmed warm-up time is the sum of all the
times programmed in the used receiver warm-up
settings packets.
EAE:
end of addresses enable. When this bit is set, the EA
bit in the Status Packet is PCD5013 set immediately after
the PCD5013 decodes the last address word in the frame
if any of the enabled PCD5013 addresses was detected in
the frame. When this bit is cleared, the EA bit is never set.
Table 12
Control packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
2
1
0
0
0
0
0
0
0
1
0
FF
7
0
0
FF
6
SPM
SBI
FF
5
PS
1
0
FF
4
PS
0
MTC
FF
3
0
0
FF
2
0
0
FF
1
0
EAE
FF
0
0
ON
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相關代理商/技術參數(shù) |
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| PCD5032D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Linear CODEC |
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