參數(shù)資料
型號(hào): PCD5013
廠商: NXP Semiconductors N.V.
英文描述: FLEX roaming decoder II
中文描述: FleX創(chuàng)建漫游解碼器二
文件頁(yè)數(shù): 19/76頁(yè)
文件大?。?/td> 270K
代理商: PCD5013
1999 Apr 12
19
Philips Semiconductors
Product specification
FLEX
roaming decoder II
PCD5013
LBP:
low battery polarity (Table 8). This bit defines the
polarity of the PCD5013’s LOBAT pin: When this bit is set,
a HIGH at input LOBAT represents a low battery condition.
The LB bit in the status packet is initialized to the inverse
(i.e. inactive) value of the LBP bit when the PCD5013 is
turned on (by setting the ON bit in the control packet).
When the PCD5013 is turned on, the first low battery
update in the status packet is sent to the host when a low
battery condition is detected on the LOBAT pin. Value
after reset = 0.
MOT:
maximum off time (Table 8). When this bit is set, the
PCD5013 assumes that the service provider leaves up to
1 minute between transmitted frames. When this bit is
clear, the PCD5013 assumes that there can be up to
4 minutes between transmitted frames. This bit has no
effect if AST in the Timing Control Packet is non-zero.
Value after reset = 0.
MTE:
minute timer enable (Table 8). When this bit is set,
a status packet is sent at one minute intervals with the
minute time-out (MT) bit in the status packet set. When
this bit is clear, the internal 1-minute timer stops counting.
See Section 8.4.8 for details of 1-minute timer operation.
Note that the minute timer is not accurate using a 160 kHz
oscillator until the IDE bit is set. Value after reset = 0.
ICO:
intermittent clock out (Table 8). When this bit is clear
and COD is clear, a 38.4 or 40 kHz (depending on the
values of IDE and DFC) signal is output on the CLKOUT
pin. When this bit is set and COD is clear, the clock is only
output on the CLKOUT pin while the receiver is not in the
Off state. The clock is output for a few cycles before the
receiver transitions from the off state and for a few cycles
after the receiver transitions to the off state (this is to insure
that the receiver receives enough clocks to detect and
process the changes to and from the off state).
The CLKOUT pin is driven LOW when it is not driving a
clock.
Note that when the clock is automatically enabled and
disabled (i.e. when ICO is set), the CLKOUT signal
transitions are clean (i.e. no pulses less than half the clock
period) when it transitions between no clock and clocked
output. This bit has no effect when COD is set. Value after
reset = 0.
8.4.5
P
ART
ID
PACKET
(ID = FFH)
The part ID packet is output by the PCD5013 SPI
whenever the SPI transmit is disabled due to the
checksum feature. The value of the part ID packet for the
PCD5013 is FF000308H.
MDL:
model (Table 9). The PCD5013 model value is 0.
CID:
compatibility ID (Table 9). This value describes other
parts with the same model number, which are compatible
with this part.
Table 7
CID Compatibilities
REV:
revision (Table 9). This identifies the manufacturing
version of the PCD5013. For the PCD5013 the value is 8.
8.4.6
C
HECKSUM PACKET
(ID = 00H)
See Table 10 for checksum packet bit assignment.
CV
: checksum value (24 bits), see Section 8.4.2.
BIT
COMPATIBILITY
VALUE FOR
PCD5013
CID
0
Alphanumeric Decoder I
CID
1
Roaming Decoder I
CID
2
Numeric Decoder
1 (true)
1 (true)
0 (false)
Table 8
Configuration packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
DFC
0
MOT
IDE
PCE
ICO
OFD
1
SP
1
0
OFD
0
SP
0
0
SME
COD
MTE
LBP
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