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參數(shù)資料
| 型號： | PC8240VTPU200ETC |
| 廠商： | Atmel Corp. |
| 英文描述： | Integrated Processor Family |
| 中文描述： | 綜合處理器系列 |
| 文件頁數(shù)： | 26/42頁 |
| 文件大小： | 421K |
| 代理商： | PC8240VTPU200ETC |
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26
PC8240
2149A–HIREL–05/02
Notes:
1. Values are in kHz unless otherwise specified.
2. FDR Hex and Divider (Dec) values are listed in corresponding order.
3. Multiple Divider (Dec) values will generate the same input frequency but each Divider (Dec) value will generate a unique
output frequency as shown in Table 15 on page 26.
Table 15 provides the two-wire interface output AC timing specifications for the PC8240.
At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V ± 5%
and LVdd = 3.3V ± 5%
Notes:
1. Units for these specifications are in SDRAM_CLK units.
2. The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in the Frequency
Divider Register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The qualified
SCL and SDA are delayed signals from what is seen in real time on the
two-wire interface
bus. The qualified SCL, SDA
signals are delayed by the SDRAM_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK clock. The resulting delay value is
added to the value in the table (where this note is referenced). See Figure 16 on page 27.
3. Since SCL and SDA are open-drain type outputs, which the PC8240 can only drive low, the time required for SCL or SDA to
reach a high level depends on external signal capacitance and pull-up resistor values.
14, 15
9216, 10240
16
21
32
64
16, 17, 3A, 3B, 3C, 3D
12288, 14336, 15360,
16384, 20480, 24576
12
16
24
48
18, 19
18432, 20480
8
10
16
32
1A, 1B, 3E, 3F
24576, 28672, 30720,
32768
6
8
12
24
1C, 1D
36864, 40960
4
5
8
16
1E, 1F
49152, 61440
3
4
6
12
Table 14.
PC8240 Maximum Two-wire Interface Input Frequency (Continued)
FDR Hex
(2)
Divider (Dec)
(2)
Max Two-wire Interface Input Frequency
(1)
SDRAM_CLK
at 25 MHz
SDRAM_CLK
at 33 MHz
SDRAM_CLK
at 50 MHz
SDRAM_CLK
at 100 MHz
Table 15.
Two-wire Interface Output AC Timing Specifications
Num
Characteristics
Min
Max
Unit
Notes
1
Start condition hold time
(FDR[5] == 0) x (D
FDR
/16)/2N +
(FDR[5] == 1) x (D
FDR
/16)/2M
–
CLKs
(1)(2)(5)
2
Clock low period
D
FDR
/2
–
CLKs
(1)(2)(5)
3
SCL/SDA rise time (from 0.5V to 2.4V)
–
–
mS
(3)
4
Data hold time
8.0 + (16 x 2
FDR[4:2]
) x (5 -
4({FDR[5],FDR[1]} == b’10) -
3({FDR[5],FDR[1]} == b’11) -
2({FDR[5],FDR[1]} == b’00) -
1({FDR[5],FDR[1]} == b’01))
–
CLKs
(1)(2)(5)
5
SCL/SDA fall time (from 2.4V to 0.5V)
< 5
ns
(4)
6
Clock high time
D
FDR
/2
–
CLKs
(1)(2)(5)
7
Data setup time (PC8240 as a master only)
(D
FDR
/2) - (Output data hold time)
–
CLKs
(1)(5)
8
Start condition setup time (for repeated start
condition only)
D
FDR
+ (Output start condition hold
time)
–
CLKs
(1)(2)(5)
9
Stop condition setup time
4.0
–
CLKs
(1)(2)
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