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參數(shù)資料
| 型號： | PC8240VTPU200ETC |
| 廠商： | Atmel Corp. |
| 英文描述： | Integrated Processor Family |
| 中文描述： | 綜合處理器系列 |
| 文件頁數(shù)： | 18/42頁 |
| 文件大小： | 421K |
| 代理商： | PC8240VTPU200ETC |
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18
PC8240
2149A–HIREL–05/02
Dynamic Electrical
Characteristics
This section provides the AC electrical characteristics for the PC8240. After fabrication,
functional parts are sorted by maximum processor core frequency as shown in Table 9,
“Clock AC Timing Specifications,” on page 18 and tested for conformance to the AC
specifications for that frequency. The processor core frequency is determined by the
bus (PCI_SYNC_IN) clock frequency and the settings of the PLL_CFG[0-4] signals.
Parts are sold by maximum processor core frequency; see “Ordering Information” on
page 41.
Table 8 provides the operating frequency information for the PC8240.
At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V
± 5%
and LVdd = 3.3V ± 5%
Note:
1. Caution: The PCI_SYNC_IN frequency and PLL_CFG[0 – 4] settings must be chosen
such that the resulting peripheral logic/memory bus frequency, CPU (core) fre-
quency, and PLL (VCO) frequencies do not exceed their respective maximum or
minimum operating frequencies. Refer to the PLL_CFG[0 – 4] signal description in
“PLL Configuration” on page 34 for valid PLL_CFG[0 – 4] settings and PCI_SYNC_IN
frequencies.
Clock AC Specifications
Table 9 provides the clock AC timing specifications as defined in Section.
At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V
± 5%
and LVdd = 3.3V ± 5%
Table 8.
Operating frequency
Characteristic
(1)
200 MHz
Unit
Min
Max
Processor Frequency (CPU)
100
200
MHz
Memory Bus Frequency
25 - 100
MHz
PCI Input Frequency
25 - 66
MHz
Table 9.
Clock AC Timing Specifications
Num
Characteristics and Conditions
(1)
Min
Max
Unit
Notes
1a
Frequency of Operation (PCI_SYNC_IN)
25
66
MHz
1b
PCI_SYNC_IN Cycle Time
40
15
ns
2, 3
PCI_SYNC_IN Rise and Fall Times
–
2.0
ns
(2)
4
PCI_SYNC_IN Duty Cycle Measured at 1.4V
40
60
%
5a
PCI_SYNC_IN Pulse Width High Measured at 1.4V
6
9
ns
(3)
5b
PCI_SYNC_IN Pulse Width Low Measured at 1.4V
6
9
ns
(3)
7
PCI_SYNC_IN Short Term Jitter (Cycle to Cycle)
–
< 500
ps
8a
PCI_CLK[0 – 4] Skew (Pin to Pin)
0
500
ps
8b
SDRAM_CLK[0 – 3] Skew (Pin to Pin)
TBD
TBD
ps
(8)
10
Internal PLL Relock Time
–
100
μs
(3)(4)(6)
15
DLL Lock Range with DLL_EXTEND = 0 disabled (Default)
0 (NT
clk
- t
loop
- t
fix0
) 7
ns
(7)
16
DLL Lock Range with DLL_EXTEND = 1 enabled
0 (NT
clk
- T
clk
/2 - t
loop
- tf
ix0
) 7
ns
(7)
17
Frequency of Operation (OSC_IN)
25
66
MHz
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