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參數(shù)資料
| 型號： | PC8240VTPU200ETC |
| 廠商： | Atmel Corp. |
| 英文描述： | Integrated Processor Family |
| 中文描述： | 綜合處理器系列 |
| 文件頁數(shù)： | 15/42頁 |
| 文件大小： | 421K |
| 代理商： | PC8240VTPU200ETC |
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15
PC8240
2149A–HIREL–05/02
The final die-junction operating temperature, is not only a function of the component-
level thermal resistance, but the system-level design and its operating conditions. In
addition to the component’s power consumption, a number of factors affect the final
operating die-junction temperature-airflow, board population (local heat flux of adjacent
components), heat sink efficiency, heat sink attach, heat sink placement, next-level
interconnect technology, system air temperature rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for
today’s microelectronic equipment, the combined effects of the heat transfer mecha-
nisms (radiation, convection and conduction) may vary widely. For these reasons, we
recommend using conjugate heat transfer models for the board, as well as, system-level
designs. To expedite system-level thermal analysis, several “compact” thermal-package
models are available within FLOTHERM
. These are available upon request.
Power Consideration
Table 5 provides
preliminary
power consumption data for the PC8240.
At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V
± 5%
and LVdd = 3.3V ± 5%
Notes:
1. The values include Vdd, AVdd, AVdd2, and LVdd but do not include I/O Supply Power, see “Power Supply Sizing” on page
36 for information on OVdd and GVdd supply power.
2. Maximum – FP power is measured at Vdd = 2.625V with dynamic power management enabled while running an entirely
cacheresident, looping, floating point multiplication instruction.
3. Maximum – INT power is measured at Vdd = 2.625V with dynamic power management enabled while running entirely
cache-resident, looping, integer instructions.
4. Power saving mode maximums are measured at Vdd = 2.625V while the device is in doze, nap, or sleep mode.
5. Typical power is measured at Vdd = AVdd = 2.5V, OVdd = 3.3V where a nominal FP value, a nominal INT value, and a
value where there is a continuous flush of cache lines with alternating ones and zeroes on 64-bit boundaries to local mem-
ory are averaged.
6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled.
7. The typical minimum I/O power values were results of the PC8240 performing cache resident integer operations at the slow-
est frequency combination of 33:66:166 (PCI:Mem:CPU) MHz.
8. The typical maximum OVdd value resulted from the PC8240 operating at the fastest frequency combination of 66:100:200
(PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeroes to PCI memory.
Table 5.
Preliminary Power Consumption
Mode
PCI Bus Clock/Memory Bus Clock
CPU Clock Frequency (MHz)
Unit
Notes
33/66/166
33/66/200
33/100/200
66/100/200
Typical
2.5
2.8
3.0
3.0
W
(1)(5)
Max – FP
3.0
3.4
3.6
3.6
W
(1)(2)
Max – INT
2.7
3.0
3.3
3.4
W
(1)(3)
Doze
1.8
2.0
2.2
2.2
W
(1)(4)(6)
Nap
700
700
900
900
mW
(1)(4)(6)
Sleep
500
500
500
800
mW
(1)(4)(6)
I/O Power Supplies
Mode
Minimum
Maximum
Unit
Notes
Typ – OVdd
200
600
mW
(7)(8)
Typ – GVdd
300
900
mW
(7)(9)
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