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參數(shù)資料
| 型號： | PC8240VTPU200ETC |
| 廠商： | Atmel Corp. |
| 英文描述： | Integrated Processor Family |
| 中文描述： | 綜合處理器系列 |
| 文件頁數(shù)： | 17/42頁 |
| 文件大小： | 421K |
| 代理商： | PC8240VTPU200ETC |
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17
PC8240
2149A–HIREL–05/02
3. See Table 7 on page 17 for the typical drive capability of a specific signal pin based upon the type of output driver associ-
ated with that pin as listed in.
4. These specifications are for the default driver strengths indicated in Table.
5. Leakage current is measured on input pins and on output pins in the high impedance state. The leakage current is mea-
sured for nominal OVdd/LVdd and Vdd or both Ovdd/LVdd and Vdd must vary in the same direction.
Table 7 provides information on the characteristics of the output drivers referenced in.
The values are from the PC8240 IBIS model (v1.0) and are not tested, for additional
detailed
information
see
the
complete
http://www.mot.com/SPS/PowerPC/ teksupport/tools/IBIS/kahlua_1.ibs.txt
IBIS
model
listing
at
Notes:
1. For DRV_PCI, I
OH
read from the listing in the pull-up mode, I(Min) column, at the 0.33V label by interpolating between the
0.3V and 0.4V table entries’ current values which correspond to the PCI V
OH
= 2.97 = 0.9*LVdd (LVdd = 3.3V) where Table
Entry Voltage = LVdd - PCI V
OH
.
2. For all others with OVdd or GVdd = 3.3V, I
OH
read from the listing in the pull-up mode, I(Min) column, at the 0.9V table entry
which corresponds to the V
OH
= 2.4V where Table Entry Voltage = O/GVdd - PCI V
OH
.
3. For GVdd = 2.5V, I
OH
read from the listing in the pull-up mode, I(Min) column, at the TBDV table entry which corresponds to
the V
OH
= TBD V where Table Entry Voltage = GVdd - V
OH
.
4. For DRV_PCI, I
OL
read from the listing in the pull-down mode, I(Max) column, at 0.33V = PCI V
OL
= 0.1*LVdd (LVdd = 3.3V)
by interpolating between the 0.3V and 0.4V table entries.
5. For all others with OVdd or GVdd = 3.3V, I
OL
read from the listing in the pull-down mode, I(Max) column, at the 0.4V table
entry.
6. For GVdd = 2.5V, I
OL
read from the listing in the pull-down mode, I(Max) column, at the TBDV table entry.
Table 7.
Drive Capability of PC8240 Output Pins
Driver Type
Programmable Output
Impedance (Ohms)
Supply
Voltage (V)
I
OH
I
OL
Unit
Notes
DRV_STD
20
OVdd = 3.3
TBD
TBD
mA
(2)(5)
40 (default)
OVdd = 3.3
TBD
TBD
mA
(2)(5)
DRV_PCI
25
LVdd = 3.3
11.0
20.6
mA
(1)(4)
LVdd = 5.0
5.6
10.3
mA
(1)(4)
50 (default)
LVdd = 3.3
5.6
10.3
mA
(1)(4)
LVdd = 5.0
5.6
10.3
mA
(1)(4)
DRV_MEM_ADDR
DRV_PCI_CLK
8 (default)
GVdd = 2.5
TBD
TBD
mA
(3)(6)
GVdd = 3.3
89.0
73.3
mA
(2)(5)
13.3
GVdd = 2.5
TBD
TBD
mA
(3)(6)
GVdd = 3.3
55.9
46.4
mA
(2)(5)
20
GVdd = 2.5
TBD
TBD
mA
(3)(6)
GVdd = 3.3
36.7
30.0
mA
(2)(5)
40
GVdd = 2.5
TBD
TBD
mA
(3)(6)
GVdd = 3.3
TBD
TBD
mA
(2)(5)
DRV_MEM_DATA
20 (default)
GVdd = 2.5
TBD
TBD
mA
(3)(6)
GVdd = 3.3
36.7
30.0
mA
(2)(5)
40
GVdd = 2.5
TBD
TBD
mA
(3)(6)
GVdd = 3.3
18.7
15.0
mA
(2)(5)
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