參數(shù)資料
型號(hào)： PC8240VTPU200ETC
廠商： Atmel Corp.
英文描述： Integrated Processor Family
中文描述： 綜合處理器系列
文件頁(yè)數(shù)： 23/42頁(yè)
文件大小： 421K
代理商： PC8240VTPU200ETC
23
PC8240
2149A–HIREL–05/02
Figure 13.
AC Test Load for the PC8240
PCI Signal Output Hold Timing
In order to meet minimum output hold specifications relative to PCI_SYNC_IN for both
33 MHz and 66 MHz PCI systems, the PC8240 has a programmable output hold delay
for PCI signals. The initial value of the output hold delay is determined by the values on
the MCP and CKE reset configuration signals. Further output hold delay values are
available by programming the PCI_HOLD_DEL value of the PMCR2 configuration
register.
Table 12 describes the bit values for the PCI_HOLD_DEL values in PMCR2.
OUTPUT
Z0 = 50
OVdd/2
RL = 50
PIN
Output measurements are made at the device pin
Table 12.
Power Management Configuration Register 2-0x72
Bit
Name
Reset value
Description
6–4
PCI_HOLD_DEL
xx0
PCI output hold delay values relative to PCI_SYNC_IN. The initial values of bits 6 and 5
are determined by the reset configuration pins MCP and CKE, respectively. As these two
pins have internal pull-up resistors, the default value after reset is 0b110.
While the minimum hold times are guaranteed at shown values, changes in the actual
hold time can be made by incrementing or decrementing the value in these bit fields of
this register via software or hardware configuration. The increment is in approximately
400 picosecond steps. Lowering the value in the three bit field decreases the amount of
output hold available.
000 66 MHz PCI. Pull-down MCP configuration pin with a 2K or less value
resistor. This setting guarantees the minimum output hold, item 13a, and
the maximum output valid, item 12a, times as specified in Figure 11 are
met for a 66 MHz PCI system. See Figure 14 on page 24.
001
010
011
100 33 MHz PCI. This setting guarantees the minimum output hold,
item 13a, and the maximum output valid, item 12a, times as specified in
Figure 11 are met for a 33 MHz PCI system. See Figure 14 on page 24.
101
110 (Default if reset configuration pins left unconnected)
111
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