
1996 Microchip Technology Inc.
Advance Information
DS40139A-page 39
PIC12C5XX
ADDWF
Syntax:
Operands:
Add W and f
[ label ADDWF f,d
0
≤
f
≤
31
d
∈ [0,1]
(W) + (f)
→
(dest)
C, DC, Z
Operation:
Status Affected:
Encoding:
Description:
0001
11df
ffff
Add the contents of the W register and
register 'f'. If 'd' is 0 the result is stored
in the W register. If 'd' is '1' the result is
stored back in register 'f'
.
1
1
Words:
Cycles:
Example:
Before Instruction
W
FSR =
After Instruction
W
FSR =
ADDWF
FSR, 0
=
0x17
0xC2
=
0xD9
0xC2
ANDLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
And literal with W
[ label ANDLW k
0
≤
k
≤
255
(W).AND. (k)
→
(W)
Z
1110
kkkk
kkkk
The contents of the W register are
AND’ed with the eight-bit literal 'k'. The
result is placed in the W register
.
1
1
Words:
Cycles:
Example:
Before Instruction
W
After Instruction
W
ANDLW
0x5F
=
0xA3
=
0x03
ANDWF
Syntax:
Operands:
AND W with f
[ label ANDWF f,d
0
≤
f
≤
31
d
∈ [0,1]
(W) .AND. (f)
→
(dest)
Z
Operation:
Status Affected:
Encoding:
Description:
0001
01df
ffff
The contents of the W register are
AND’ed with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
'1' the result is stored back in register 'f'
.
1
1
Words:
Cycles:
Example:
Before Instruction
W
FSR =
After Instruction
W
FSR =
ANDWF
FSR,
1
=
0x17
0xC2
=
0x17
0x02
BCF
Syntax:
Operands:
Bit Clear f
[ label BCF f,b
0
≤
f
≤
31
0
≤
b
≤
7
0
→
(f<b>)
None
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
0100
bbbf
ffff
Bit 'b' in register 'f' is cleared.
1
1
BCF
FLAG_REG, 7