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| 型號： | P12C508 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 8-Pin, 8-Bit CMOS Microcontroller |
| 中文描述： | 8引腳，8位CMOS微控制器 |
| 文件頁數(shù)： | 33/84頁 |
| 文件大?。?/td> | 526K |
| 代理商： | P12C508 |
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1996 Microchip Technology Inc.
Advance Information
DS40139A-page 33
PIC12C5XX
7.6.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms,
(with no prescaler). If a longer time-out period is
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT (under software control)
by writing to the OPTION register. Thus, time-out a
period of a nominal 2.3 seconds can be realized.
These periods vary with temperature, V
DD
and part-to-
part process variations (see DC specs).
Under worst case conditions (V
DD
= Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
7.6.2
WDT PROGRAMMING CONSIDERATIONS
The
CLRWDT
instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it
from timing out and generating a device RESET.
The
SLEEP
instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum SLEEP time before a WDT wake-up reset.
FIGURE 7-12: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 7-5:
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2 Bit 1
Bit 0
Value on
Power-On
Reset
Value on
MCLR and
WDT Reset
Value on
Wake-up on
Pin Change
N/A
OPTION
GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer,
—
= unimplemented, read as '0',
u
= unchanged
1
0
1
0
From Timer0 Clock Source
(Figure 6-5)
To Timer0 (Figure 6-4)
Postscaler
WDT Enable
EPROM Bit
PSA
WDT
Time-out
PS2:PS0
PSA
MUX
8 - to - 1 MUX
M
U
X
Watchdog
Timer
Note: T0CS, T0SE, PSA, PS2:PS0
are bits in the OPTION register.
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