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| 型號： | P12C508 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 8-Pin, 8-Bit CMOS Microcontroller |
| 中文描述： | 8引腳，8位CMOS微控制器 |
| 文件頁數(shù)： | 19/84頁 |
| 文件大?。?/td> | 526K |
| 代理商： | P12C508 |
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1996 Microchip Technology Inc.
Advance Information
DS40139A-page 19
PIC12C5XX
5.0
I/O PORT
As with any other register, the I/O register can be
written and read under program control. However,
read instructions (e.g.,
MOVF GPIO,W
) always read the
I/O pins independent of the pin’s input/output modes.
On RESET, all I/O ports are defined as input (inputs
are at hi-impedance) since the I/O control registers are
all set. GP0 and GP1 can be programmed in software
with weak pull-ups.
5.1
GPIO
GPIO is an 8-bit I/O register. Only the low order 6 bits
are used (GP5:GP0). Bits 7 and 6 are unimplemented
and read as '0's. Please note that GP3 is an input only
pin. The configuration word can set several I/O’s to
alternate functions. When acting as alternate functions
the pins will read as ‘0’ during port read. Pins GP0,
GP1, and GP3 can be configured with weak pull-ups
and also with wake-up on change. The wake-up on
change and weak pull-up functions are not pin
selectable. If pin 4 is configured as MCLR, weak pull-
up is always on and wake-up on change for this pin is
not set.
5.2
TRIS Register
The output driver control register is loaded with the
contents of the W register by executing the
TRIS
f
instruction. A '1' from a TRIS register bit puts the
corresponding output driver in a hi-impedance mode.
A '0' puts the contents of the output data latch on the
selected pins, enabling the output buffer. The
exceptions are GP3 which is input only and GP2 which
may be controlled by the option register, see
Section 4.4.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon RESET.
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
5.3
I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins, except GP3 which is input
only, may be used for both input and output
operations. For input operations these ports are non-
latching. Any input must be present until read by an
input instruction (e.g.,
MOVF GPIO,W
). The outputs are
latched and remain unchanged until the output latch is
rewritten. To use a port pin as output, the
corresponding direction control bit in TRIS must be
cleared (= 0). For use as an input, the corresponding
TRIS bit must be set. Any I/O pin (except GP3) can be
programmed individually as input or output.
FIGURE 5-1:
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Note 1: I/O pins have protection diodes to V
DD
and V
SS
.
Data
Bus
Q
D
Q
CK
Q
D
Q
CK
P
N
WR
Port
TRIS ‘f’
Data
Latch
TRIS
Latch
RD Port
V
SS
V
DD
I/O
pin
(1)
W
Reg
Reset
TABLE 5-1:
SUMMARY OF PORT REGISTERS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2 Bit 1 Bit 0
Value on
Power-On
Reset
Value on
MCLR and
WDT Reset
Value on
Wake-up on
Pin Change
N/A
TRIS
I/O control registers
--11 1111
--11 1111
--11 1111
N/A
OPTION
GPWU
GPPU
T0CS T0SE PSA
PS2
PS1 PS0
1111 1111
1111 1111
1111 1111
03H
STATUS
GPWUF
—
PA0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
100q quuu
06h
GPIO
—
—
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
--uu uuuu
--uu uuuu
Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0',
x
= unknown,
u
= unchanged,
q = see tables in Section 7.7 for possible values.
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