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| 型號： | OX16PCI954 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated Quad UART and PCI interface |
| 中文描述： | 綜合四UART和PCI接口 |
| 文件頁數(shù)： | 55/72頁 |
| 文件大?。?/td> | 656K |
| 代理商： | OX16PCI954 |
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DSR[2]: INT#
logic 0
A parallel port interrupt is pending.
logic 1
No parallel port interrupt is pending.
This bit is activated (set low) on a rising edge of the ACK#
pin. It is de-activated (set high) after reading the DSR.
DSR[3]: ERR#
logic 0
The ERR#input is low.
logic 1
The ERR#input is high.
DSR[4]: SLCT
logic 0
The SLCT input is low.
logic 1
The SLCT input is high.
DSR[5]: PE
logic 0
The PE input is low.
logic 1
The PE input is high.
DSR[6]: ACK#
logic 0
The ACK#input is low.
logic 1
The ACK#input is high.
DSR[7]: nBUSY
logic 0
The BUSY input is high.
logic 1
The BUSY input is low.
Data Sheet Revision 1.3
Page 55
OX16PCI954
OXFORD SEMICONDUCTOR LTD.
9.3.3
DCR is located at offset 002h in the lower block. It is a
read-write register which controls the state of the peripheral
inputs and enables the peripheral interrupt. When reading
this register, bits 0 to 3 reflect the actual state of STB#
AFD# INIT#and SLIN#pins respectively. When in EPP
mode, the WRITE# DATASTB#AND ADDRSTB#pins are
driven by the EPP controller, although writes to this register
will override the state of the respective lines.
DCR[0]: nSTB#
logic 0
Set STB#output to high (inactive).
logic 1
Set STB#output to low (active).
During an EPP address or data cycle the WRITE#pin is
driven by the EPP controller, otherwise it is inactive.
DCR[1]: nAFD#
logic 0
Set AFD#output to high (inactive).
logic 1
Set AFD#output to low (active).
During an EPP address or data cycle the DATASTB#pin is
driven by the EPP controller, otherwise it is inactive.
DCR[2]: INIT#
logic 0
Set INIT#output to low (active).
logic 1
Set INIT#output to high (inactive).
Device control register ‘DCR’
DCR[3]: nSLIN#
logic 0
Set SLIN#output to high (inactive).
logic 1
Set SLIN#output to low (active).
During an EPP address or data cycle the ADDRSTB#pin is
driven by the EPP controller, otherwise it is inactive.
DCR[4]: ACK Interrupt Enable
logic 0
ACK interrupt is disabled.
logic 1
ACK interrupt is enabled.
DCR[5]: DIR
logic 0
PD port is output.
logic 1
PD port is input.
This bit is overridden during an EPP address or data cycle,
when the direction of the port is controlled by the bus
access (read/write)
DCR[7:6]: Reserved
These bits are reserved and always set to “00”.
9.3.4
EPP address register ‘EPPA’
EPPA is located at offset 003h in lower block, and is only
used in EPP mode. A byte written to this register will be
transferred to the peripheral as an EPP address by the
hardware. A read fromthis register will transfer an address
fromthe peripheral under hardware control.
9.3.5
The EPPD registers are located at offset 004h-007h of the
lower block, and are only used in EPP mode. Data written
or read fromthese registers is transferred to/fromthe
peripheral under hardware control.
EPP data registers ‘EPPD1-4’
9.3.6
The Extended control register is located at offset 002h in
upper block. It is used to configure the operation of the
parallel port.
ECR[4:0]: Reserved
These bits are reserved and must always be set to
“00001”.
ECR[7:5]: Mode
These bits define the operational mode of the parallel port.
logic ‘000’
SPP
logic ‘001’
PS2
logic ‘010’
Reserved
logic ‘011’
Reserved
logic ‘100’
EPP
logic ‘101’
Reserved
logic ‘110’
Reserved
logic ‘111’
Reserved
Extended control register ‘ECR’
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