參數(shù)資料
型號(hào)： OX16PCI954
廠商： Electronic Theatre Controls, Inc.
英文描述： Integrated Quad UART and PCI interface
中文描述： 綜合四UART和PCI接口
文件頁(yè)數(shù)： 53/72頁(yè)
文件大?。?/td> 656K
代理商： OX16PCI954
9 B
IDIRECTIONAL
P
ARALLEL
P
ORT
Data Sheet Revision 1.3
Page 53
OX16PCI954
OXFORD SEMICONDUCTOR LTD.
9.1
Operation and Mode selection
The OX16PCI954 offers a compact, low power, IEEE-1284
(EPP-only) compliant host-interface parallel port, designed
to interface to many peripherals such as printers, scanners
and external drives. It supports compatibility modes, SPP,
NIBBLE and PS2, as well as EPP mode. The register set is
compatible with the Mcrosoft
register definition. To
enable the parallel port function, the Mode[1:0] pins should
be set to ‘01’. The systemcan access the parallel port via
two 8-byte blocks of I/O space; BAR0 contains the address
of the basic parallel port registers, BAR1 contains the
address of the upper registers. These are referred to as the
‘lower block’ and ‘upper block’ in this section. If the upper
block is located at an address 0x400 above the lower
block, generic PC device drivers can be used to configure
the port, as the addressable registers of legacy parallel
ports always have this relationship. If not, a customdriver
will be needed.
9.1.1
SPP (output-only) is the standard implementation of a
simple parallel port. In this mode, the PD lines always drive
the value in the PDR register. All transfers are done under
software control. Input must be performed in nibble mode.
Generic device driver-software may use the address in I/O
space encoded in BAR0 of function 1 to access the parallel
port. The default configuration allocates 8 bytes to BAR0 in
I/O space.
SPP mode
9.1.2
This mode is also referred to as bi-directional or compatible
parallel port. In this mode, directional control of the PD
lines is possible by setting & clearing DCR[5]. Otherwise
operation is simlar to SPP mode.
PS2 mode
9.1.3
To use the Enhanced Parallel Port ‘EPP’ the mode bits
(ECR[7:5]) must be set to ‘100’. The EPP address and data
port registers are compatible with the IEEE 1284 definition.
A write or read to one of the EPP port registers is passed
through the parallel port to access the external peripheral.
In EPP mode, the STB# INIT# AFD# AND SLIN# pins
EPP mode
change fromopen-drain outputs to active push-pull (totem
pole) drivers (as required by IEEE 1284) and the pins
ACK# AFD# BUSY, SLIN#and STB#are redefined as
INTR# DATASTB# WAIT# ADDRSTB# and WRITE#
respectively.
An EPP port access begins with the host reading or writing
to one of the EPP port rgisters. The device automatically
buffers the data between the I/O registers and the parallel
port depending on whether it is a read or a write cycle.
When the peripheral is ready to complete the transfer it
takes the WAIT#status line high. This allows the host to
complete the EPP cycle.
If a faulty or disconnected peripheral failed to respond to an
EPP cycle the host would never see a rising edge on
WAIT# and subsequently lock up. A built-in time-out facility
is provided in order to prevent this fromhappening. It uses
an internal timer which aborts the EPP cycle and sets a
flag in the PSR register to indicate the condition. When the
parallel port is not in EPP mode the timer is switched off to
reduce current consumption. The host time-out period is
10
μ
s as specified with the IEEE-1284 specification.
The register set is compatible with the Mcrosoft
register
definition. Assumng that the upper block is located 400h
above the lower block, the registers are found at offset
000-007h and 400-402h.
9.1.4
The Extended Capabilities Port ‘ECP’ mode is not
supported.
9.2
Parallel port interrupt
ECP mode (not supported)
The parallel port interrupt is asserted on INTB#(or INTA#if
specified with the serial EEPROM). It is enabled by setting
DCR[4]. When DCR[4] is set, an interrupt is asserted on
the rising edge of the ACK#(INTR#) pin and held until the
status register is read, which resets the INT#status bit
(DSR[2]).
相關(guān)PDF資料
PDF描述
OX16PCI954-TQC60-A Integrated Quad UART and PCI interface
OX4240 OCXO
OX1040 OCXO
OX1041 OCXO
OX1042 OCXO
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OX16PCI954_05 制造商:OXFORD 制造商全稱(chēng):OXFORD 功能描述:Integrated Quad UART and PCI interface
OX16PCI954-TQA1G 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI bridge to quad serial & para. port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
OX16PCI954-TQC60-A 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Integrated Quad UART and PCI interface
OX16PCI954-TQC60-A1 制造商:OXFORD 制造商全稱(chēng):OXFORD 功能描述:Integrated Quad UART and PCI interface
OX16PCI958 制造商:OXFORD 制造商全稱(chēng):OXFORD 功能描述:Octal UART with PCI Interface
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*