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| 型號： | OX16PCI954 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated Quad UART and PCI interface |
| 中文描述： | 綜合四UART和PCI接口 |
| 文件頁數(shù)： | 22/72頁 |
| 文件大小： | 656K |
| 代理商： | OX16PCI954 |
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Data Sheet Revision 1.3
Page 22
OX16PCI954
OXFORD SEMICONDUCTOR LTD.
6.4.4
Bits
3:0
Local Bus Timing Parameter register 2 ‘LT2’ (Offset 0x0C):
Description
Write Data Bus Assertion. This register defines the number of clock
cycles after the Reference Cycle when the LBD pins actively drive the
data bus during a write operation to the Local Bus.
1
Write Data Bus De-assertion. This register defines the number of clock
cycles after the Reference Cycle when the LBD pins go high-impedance
during a write operation to the Local Bus.
1,2
Read Data Bus Assertion. This register defines the number of clock
cycles after the Reference Cycle when the LBD pins actively drive the
data bus at the end of a read operation fromthe Local Bus.
1
Read Data Bus De-assertion. This register defines the number of clock
cycles after the Reference Cycle when the LBD pins go high-impedance
during at the beginning of a read cycle fromthe Local Bus.
1
Reserved.
IO Space Block Size of BAR0 in Function1.
000 = Reserved
001 = 4 Bytes
010 = 8 Bytes
011 = 16 Bytes
Local Bus Chip–select Parameter ‘Lower-Address-CS-Decode’.
2
IO space in 8-bit Local Bus
Read/Write
EEPROM
W
Reset
0h
PCI
RW
7:4
W
RW
Fh
11:8
W
RW
4h
(2h for
parallel port)
0h
15:12
W
RW
19:16
22:20
-
R
R
0h
‘100’
(=‘010’
for parallel
port)
W
100 = 32 Bytes
101 = 64 Bytes
110 = 128 Bytes
111 = 256 Bytes
26:23
W
RW
Memory space and IO space in
32-bit Local Bus
0000 = A4
0001 = A5
0010 = A6
0011 = A7
0100 = A8
0101 = A9
0110 = A10
0111 = A11
0000 = A2
0001 = A3
0010 = A4
0011 = A5
0100 = A6
0101 = A7
0110 = A8
0111 = A9
Memory Space Block Size of BAR1 in Function1 (Mode[1:0]=‘11’, i.e. 32-
bit Local Bus).
00 = 4 Kbytes
01 = 16 Kbytes
When 8-bit Local Bus or Parallel Port is selected (Mode[1:0]=‘00’ or ‘01’),
the Memory Block size is fixed at 4K and these bits are ignored.
Local Bus Software Reset. When this bit is a 1 the Local Bus reset pin is
activated. When this bit is a 0 the Local Bus reset pin is de-activated.
3
Local Bus Clock Enable. When this bit is a 1 the Local Bus clock (LBCK)
pin is enabled. When this bit is a 0 LBCK pin is permanently low. The
Local Bus Clock is a buffered PCI clock.
Bus Interface Type. When low (=0) the Local Bus is configured to Intel-
type operation, otherwise it is configured to Motorola-type operation.
Note that when Mode[1:0] is ‘01’, this bit is hard wired to 0.
1000 = Res
1001 = Res
1010 = Res
1011 = Res
1100 = Res
1101 = Res
1110 = Res
1111 = Res
1000 = A12
1001 = A13
1010 = A14
1011 = Res
1100 = Res
1101 = Res
1110 = Res
1111 = Res
‘0001’
(=‘0010’
for parallel
port)
28:27
W
R
00
10 = Reserved
11 = Reserved
29
-
RW
0
30
W
RW
0
31
W
RW
0
Note 1:
Only values in the range of 0 to Ah (0-10 decimal) are valid. Other values are reserved as writing higher values causes the PCI interface to retry all
accesses to the Local Bus as it is unable to complete the transaction in 16 PCI clock cycles.
Note 2:
The Lower-Address-CS-Decode parameter is described in sections 6.3.2 & 6.3.4. These bits are unused for Memory access to the 8-bit Local Bus
which uses a fixed decoding to allocate 1K regions to 4 chip selects. For further information on the Local bus, see section 8.
Note 3:
Local Bus, UARTs and the Parallel Port are all reset with PCI reset. In Addition, the user can issue the Software Reset Command.
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