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參數(shù)資料
| 型號： | OV6630 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA |
| 中文描述： | 單芯片CMOS到岸價格彩色數(shù)碼攝像機 |
| 文件頁數(shù)： | 24/29頁 |
| 文件大?。?/td> | 206K |
| 代理商： | OV6630 |
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S INGLE IC CMOS COLOR AND B/W DIGIT AL CAMERAS
March 4, 2000
Version 1.0
24
by FSD[1:0]. It is disabled in OFF and FRAME mode. The purpose of FSD[7:2] is to
divide the video signal into programmed number of time slots, and allows HREF to
be active only one field in every FSD[7:2] fields. It does not affect the video data or
pixel rate. FSD[7:2] disables digital data output, there is only black reference level at
the output. FSD[7:2]=1 outputs every field. FSD[7:2]=2 outputs one field and
disables one field, etc.
FSD[1:0] – field mode selection. Each frame consists of two fields: Odd and Even,
FSD[1:0] define the assertion of HREF in relation to the two fields.
“00” – OFF mode; HREF is not asserted in both fields, one exception is the single
frame transfer operation (see the description for the register 13)
“01” – ODD mode; HREF is asserted in odd field only.
“10” – EVEN mode; HREF is asserted in even field only.
“11” – FRAME mode; HREF is asserted in both odd field and even field. FSD[7:2]
disabled.
Horizontal HREF start
HS[7:0] – selects the starting point of HREF window, each LSB represents two pixels
for CIF resolution mode, one pixels for QCIF resolution mode, this value is set based
on an internal column counter, the default value corresponds to 352 horizontal
window. Maximum window size is 356. See window description below. HS[7:0]
programmable range is [38] - [EB], and should less than HE[7:0]. HS[7:0] should be
programmable to value larger than or equal to [38]. Value larger than [EC] is invalid.
See window description below.
Horizontal HREF end
HE[7:0] – selects the ending point of HREF window, each LSB represents two pixels
for full resolution and one pixels for QCIF resolution, this value is set based on an
internal column counter, the default value corresponds to the last available pixel. The
HE[7:0] programmable range is [39] - [EC]. HE[7:0] should be larger than HS[7:0]
and less than or equal to [EC]. Value larger than [EC] is invalid. See window
description below.
Vertical line start
VS[7:0] – selects the starting row of vertical window, in full resolution mode, each LSB
represents 1 scan line in one frame. See window description below. Min. is [03],
max. is [93] and should less than VE[7:0].
Vertical line end
VE[7:0] – selects the ending row of vertical window, in full resolution mode, each LSB
represents 1 scan line in one frame, see window description below. Min. is [04], max.
is [94] and should larger than VS[7:0].
Pixel shift
PS[7:0] – to provide a way to fine tune the output timing of the pixel data relative to
that of HREF, it physically shifts the video data output time late in unit of pixel clock
as shown in the figure below. This function is different from changing the size of the
window as defined by HS[7:0] and HE[7:0] in registers 17 and 18. Higher than
default number delay the pixel output relative to HREF. The highest number is “FF”
and the maximum shift number is delay 256 pixels.
Manufacture ID byte: High
MIDH[7:0] – read only, always returns “7F” as manufacturer’s ID no.
Manufacture ID byte: Low
MIDL[7:0] – read only, always returns “A2” as manufacturer’s ID no.
Reserved
Common control E
COME[7] – HREF pixel number selection. “1” - HREF include 704 PCLK, every data
output twice.
COME[6] – reserved.
COME[5] – “1” First stage aperture correction enable. Correction strength will be
decided by register [07]. “0” disable first stage aperture correction.
COME[4] – “1” Second stage aperture correction enable. Correction strength and
threshold value will be decided by COMF[7] ~ COMF[4].
COME[3] – AWB smart mode enable. 1 – do not count pixels that their luminance level
are not in the range defined in register [0F]. 0 - count all pixels to get AWB result.
Valid only when COMB[0]=1 and COMA[2]=1
17
HREFST
38
RW
18
HREFEND
EA
RW
19
VSTRT
03
RW
1A
92
RW
1B
PSHFT
00
RW
1C
MIDH
7F
R
1D
MIDL
A2
R
1E-1F
20
Rsvd 1E-1F
COME
××
00
RW
RW
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