參數(shù)資料
型號(hào)： OV6630
廠商： Electronic Theatre Controls, Inc.
英文描述： SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA
中文描述： 單芯片CMOS到岸價(jià)格彩色數(shù)碼攝像機(jī)
文件頁(yè)數(shù)： 12/29頁(yè)
文件大?。?/td> 206K
代理商： OV6630
S INGLE IC CMOS COLOR AND B/W DIGIT AL CAMERAS
Executing a software power down through the I
2
C interface suspends
internal circuit activity, but does not halt the device clock. The current
requirements drop to less than 1mA in this mode.
March 4, 2000
Version 1.0
12
1.2.11
Two methods are provided to configure OV6630/OV6130 for specific
application requirements.
At power up, OV6630/OV6130 reads the status of certain pins to
determine what, if any, power up pin programming default settings
are requested. Once the reading of the external pins status is
completed, the device configures its internal registers according to the
Configure OV6630/OV6130
specified pins. Not all device functions are available for configuration
through external pins. Power up pin programming occurs in 1024
system clock cycles.
A more flexible and comprehensive method to configure
OV6630/OV6130 is to use its on-chip I
2
C register programming
capability. The I
2
C interface provides access to all of the device’s
programmable internal registers. See I2C Bus Protocol Format for
further details about using the I
C interface on the OV6630/OV6130
camera device.
CLK
HSYNC
VSYNC
1 Line=472 T
CLK
1 Frame=625 x 472 T
CLK
T
CLK
T
HS
T
VS
Notes:
T
> 6 T
(2), T
< T
VS
< 472 T
CLK
HSYNC period is (472 T
)
VSYNC period is (625 x 472 T
)
OV6630/OV6130 will be stable after 1 field (2nd VSYNC)
Figure 6. Slave Mode External Sync Timing
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