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參數(shù)資料
| 型號： | OV6630 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE-CHIP CMOS CIF COLOR DIGITAL CAMERA |
| 中文描述： | 單芯片CMOS到岸價格彩色數(shù)碼攝像機 |
| 文件頁數(shù)： | 19/29頁 |
| 文件大?。?/td> | 206K |
| 代理商： | OV6630 |
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S INGLE IC CMOS COLOR AND B/W DIGIT AL CAMERAS
3 I
2
C Bus
March 4, 2000
Version 1.0
19
Many of the functions and configuration registers in the
OV6630/OV6130 image sensors are available through the I
2
C
interface. The I
2
C port is enabled by asserting the I2CB line (pin 12)
through a 10K
resistor to V
DD
. When the I
2
C capability is enabled
(I2CB = 1), the OV6630/OV6130 imager operates as a slave device
that supports up to 400 KBps serial transfer rate using a 7-bit
address/data transfer protocol.
– SLAVE TRANSMIT
– MASTER TRANSMIT
– MASTER INITIATE
MASTER TRANSMIT, SLAVE RECEIVE (WRITE CYCLE)
MASTER TRANSMIT, SLAVE RECEIVE (DUMMY WRITE CYCLE)
S
SLAVE ID (7BITS)
RW
A
SUB-ADDRESS (8BITS)
A
P
START
MSB
LSB=0
ACK STOP
1ST BYTE
2ND BYTE
S
SLAVE ID (7BITS)
RW
A
SUB-ADDRESS (8BITS)
A
DATA (8BITS)
A
P
START
MSB
LSB=0
ACK
ACK STOP
1ST BYTE
2ND BYTE
3RD BYTE
MASTER RECEIVE, SLAVE TRANSMIT (READ CYCLE)
S
SLAVE ID (7BITS)
RW
A
DATA (8BITS)
A
DATA (8BITS)
1
P
START
MSB
LSB=1
ACK
NO ACK IN
LAST BYTE
STOP
1ST BYTE
2ND BYTE
3RD BYTE
SLAVE ID - 110CCC0X
S - START CONDITION
A - ACKNOWLEDGE BIT
P - STOP CONDITION
CS2 (PIN 35)
CS1 (PIN 37)
CS0 (PIN 34)
X - RW BIT, 1:READ, 0:WRITE
Figure 8. I
2
C Bus Protocol Format
3.1
In I
2
C operation, the master must perform the following operations:
I2C Bus Protocol Format
-
Generate the start/stop condition
-
Provide the serial clock on SCL
-
Place the 7-bit slave address, the RW bit, and the 8-bit sub-
address on SDA
The receiver must pull down SDA during the acknowledge period.
During the write cycle, OV6630/OV6130 returns acknowledge and,
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