參數(shù)資料
型號： ORT8850H
英文描述： Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）8通道x 850 Mbits /秒背板收發(fā)器
文件頁數(shù)： 77/112頁
文件大?。?/td> 2417K
代理商： ORT8850H
Agere Systems Inc.
77
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Pin Information
(continued)
Package Pinouts
Table 33 and Table 34 provide the package pin and pin
function for the ORT8850 FPSC and packages. The
bond pad name is identified in the PIO nomeclature
used in the
ORCA
Foundry design editor. The Bank
column provides information as to which output voltage
level bank the given pin is in. The Group column pro-
vides information as to the group of pins the given pin
is in. This is used to show which VREF pin is used to
provide the reference voltage for single-ended limited-
swing I/Os. If none of these buffer types (such as
SSTL, GTL, HSTL) are used in a given group, then the
VREF pin is available as an I/O pin.
When the number of FPGA bond pads exceeds the
number of package pins, bond pads are unused. When
the number of package pins exceeds the number of
bond pads, package pins are left unconnected (no con-
nects). When a package pin is to be left as a no con-
nect for a specific die, it is indicated as a note in the
device column for the FPGA. The tables provide no
information on unused pads.
The pinouts for both the ORT8850H and ORT8850L in
the 680 PBGAM package are shown in Table 32. In
order to allow pin-for-pin compatible board layouts that
can accommodate both devices, some key compatibil-
ity issues include the following.:
I
Unused Pins.
As shown in Table 32, there are 19
balls that are not available in the ORT8850L, but are
available in the ORT8850H. These user I/Os should
not be used if the ORT8850L may be used.
I
Shared Control Signals on I/O Registers.
The
ORCA
Series 4 architecture shares clock and control
signals between two adjacent I/O pads. If I/O regis-
ters are used, incompatibilities may arise between
ORT8850L and ORT8850H when different clock or
control signals are needed on adjacent package
pins. This is because one device may allow indepen-
dent clock or control signals on these adjacent pins,
while the other may force them to be the same.
There are two ways to avoid this issue.
—
Always keep an open bonded pin (non-bonded
pins for the ORT8850L do not count) between
pins that require different clock or control signals.
Note that this open pin can be used to connect
signals that do not require the use of I/O registers
to meet timing.
—
Place and route the design in both the ORT8850H
and ORT8850L to verify both produce valid
designs. Note that this method guarantees the
current design, but does not necessarily guard
against issues that can occur when design
changes are made that affect I/O registers.
—
2X/4X I/O Shift Registers.
If 2X I/O shift registers
or 4X I/O shift registers are used in the design,
this may cause incompatibilities between the
ORT880L and ORT8850H because only the A and
C I/Os in a PIC support 2X I/O shift registers and
only A I/Os supports 4X I/O shift register mode. A
and C I/Os are shown in the following pinout
tables under the I/O pad columns as those ending
in A or C.
I
Edge Clock Input Pins.
The input buffers for fast
edge clocks are only available at the C I/O pad. The
C I/Os are shown in the following pinout tables under
the I/O pad colums as those ending in C.
I
Unused Pins.
One of the incompatibilities is due to
the fact that the ORT8850L is a much smaller array
and does not provide as many programmable IOs
(PIOs). Table 32 shows a list of bonded ORT8850H
PIOs that are unused in the ORT8850L.
Table 32. ORT8850H Pins That Are Unused in
ORT8850L
Users should avoid using these pins if they plan to
migrate their ORT8850H design to an ORT8850L.
BGA Ball Bonds
K4
M5
R5
T5
W4
AA2
Y4
AC4
AD5
AG1
AP4
AK10
AK11
AM9
AN9
AM14
AN14
D11
E13
ORT8850H PIOs
PL11A
PL13A
PL20A
PL21A
PL27A
PL28A
PL29A
PL35A
PL37A
PL38A
PB3A
PB9A
PB10A
PB11A
PB12A
PB19A
PB20A
PT12A
PT11A
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ORT8850H-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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