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參數(shù)資料
| 型號(hào)： | ORT8850H |
| 英文描述： | Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器 |
| 文件頁數(shù)： | 37/112頁 |
| 文件大?。?/td> | 2417K |
| 代理商： | ORT8850H |
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Agere Systems Inc.
37
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
RapidIO
Interface to Pi-Sched
(continued)
Table 8.
RapidIO
Signals to/from FPGA
Interface Name
(All End with _A, _B, or
_C Depending on
Channel)
Receive Cell Interface
ZRXD<31:0>
From
FPGA
To FPGA
Description
—
32
32-bit data from the receive module. The bus contains four
octets and reflects data received via the high-speed RXD data
bus.
Indicates the presence of the first octet of a new cell within the
first 32-bit data word on the bus RXD in bit positions [31:24].
Indicates a minimum cell violation within the receive module.
This signal will transition active-high coincident with RXSOC.
An active state signals the new cell overran the previous cell,
and the previous cell is in violation of the minimum cell size.
Signals an alignment error. An active state signals RXSOC was
captured on a negative RXCLK edge. The violation condition
on this signal will stay high for a single
WRXCLK_[chan]_FPGA cycle coincident with RXSOC.
Indicates the loss or absence of a clock on the LVDS clock
(RXCLK). This signal will be present for the duration of the
absence of the clock, following a period to validate its absence.
System cell processing enable. After reset is released, drive
this signal high when the
RapidIO
is ready to transmit cells.
This signal should be active after all control signals into the
RapidIO
are stable.
Synchronous reset for all memory elements clocked by
WRXCLK_[chan]_FPGA (derived from PLL).
Derived from high-speed LVDS clock RXCLK (RXCLK/2).
ZRXSOC
—
1
ZRXSOCVIOL
—
1
ZRXALNVIOL
—
1
ZCLKSTAT
—
—
CSYSENB
1
—
RSTN_RX
1
—
WRXCLK_[chan]_FPGA
Transmit Cell Interface
UTXD[31:0]
—
1
32
—
Transmit data bs containing four octets synchronized with the
rising edge of the 60 MHz
—
146 MHz WUTXCLK_FPGA
(derived from PLL) is clocked into the transmit FIFO within the
RapidIO
.
Start of cell, originating within core, synchronized with the ris-
ing edge of WUTXCLK_FPGA into the transmit FIFO. Indicates
the first data word on TXD bus includes the first octet of a new
cell in bit positions [31:24].
Synchronous reset for all memory elements in the WUTXCLK
domain.
Output 3-state enable (active-low). When active, the TXD,
TXSOC, and TXCLK LVDS drivers are 3-stated.
0: 3-state TXD, TXSOC and TXCLK drivers.
1: Normal operation.
UTXSOC
1
—
RSTN_UTX
1
—
UTXTRISTN
1
—
FPGA Interface Clocks (Common to All Channels)
WUTXCLK_FPGA
—
1
One X core clock generated from an internal PLL circuit. Syn-
chronous to UTXD and UTXSOC data inputs.
1/2 X main PLL output clock. Phase-aligned with PFCLK. Nom-
inal frequency = 30 MHz to 73 MHz. Duty cycle spec = 47%/
53%.
HALFCLK_FPGA
—
1
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