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| 型號： | ORT8850H |
| 英文描述： | Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）8通道x 850 Mbits /秒背板收發(fā)器 |
| 文件頁數(shù)： | 32/112頁 |
| 文件大小： | 2417K |
| 代理商： | ORT8850H |
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32
Agere Systems Inc.
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Backplane Transceiver Core Detailed
Description
(continued)
Pointer Interpreter State Machine.
The pointer inter-
preter
’
s highest priority is to maintain accurate data
flow (i.e., valid SPE only) into the elastic store. This will
ensure that any errors in the pointer value will be cor-
rected by a standard, fully SONET compliant, pointer
interpreter without any data hits. This means that error
checking for increment, decrement, and new data flag
(NDF) (i.e., 8 of 10) is maintained in order to ensure
accurate data flow. A single valid pointer (i.e., 0
—
782)
that differs from the current pointer will be ignored. Two
consecutive incoming valid pointers that differ from the
current pointer will cause a reset of the J1 location to
the latest pointer value (the generator will then produce
an NDF). This block is designed to handle single bit
errors without affecting data flow or changing state.
The pointer interpreter has only three states (NORM,
AIS, and CONC). NORM state will begin whenever two
consecutive NORM pointers are received. If two con-
secutive NORM pointers that both differ from the cur-
rent offset are received, then the current offset will be
reset to the last received NORM pointer. When the
pointer interpreter changes its offset, it causes the
pointer generator to receive a J1 value in a new posi-
tion. When the pointer generator gets an unexpected
J1, it resets its offset value to the new location and
declares an NDF. The interpreter is only looking for two
consecutive pointers that are different from the current
value. These two consecutive NORM pointers do not
have to have the same value. For example, if the cur-
rent pointer is ten and a NORM pointer with offset of 15
and a second NORM pointer with offset of 25 are
received, then the interpreter will change the current
pointer to 25. The receipt of two consecutive CONC
pointers causes CONC state to be entered. Once in
this state, offset values from the head of the concate-
nation chain are used to determine the location of the
STS SPE for each STS in the chain. Two consecutive
AIS pointers cause the AIS state to occur. Any two con-
secutive normal or concatenation pointers will end this
AIS state. This state will cause the data leaving the
pointer generator to be overwritten with 0xFF.
5-8589 (F)
Figure 13. Pointer Mover State Machine
Pointer Generator.
The pointer generator maps the
corresponding bytes into their appropriate location in
the outgoing byte stream. The generator also creates
offset pointers based on the location of the J1 byte as
indicated by the pointer interpreter. The generator will
signal NDFs when the interpreter signals that it is com-
ing out of AIS state. The pointer generator resets the
pointer value and generates NDF every time a byte
marked J1 is read from the elastic store that doesn
’
t
match the previous offset.
Increment and decrement signals from the pointer
interpreter are latched once per frame on either the F1
or E2 byte times (depending on collisions); this ensures
constant values during the H1 through H3 times. The
choice of which byte time to do the latching on is made
once when the relative frame phases (i.e., received
and system) are determined. This latch point is then
stable unless the relative framing changes and the
received H byte times collide with the system F1 or E2
times, in which case the latch point would be switched
to the collision-free byte time.
There is no restriction on how many or how often incre-
ments and decrements are processed. Any received
increment or decrement is immediately passed to the
generator for implementation regardless of when the
last pointer adjustment was made. The responsibility
for meeting the SONET criteria for maximum frequency
of pointer adjustments is left to an upstream pointer
processor.
When the interpreter signals an AIS state, the genera-
tor will immediately begin sending out 0xFF in place of
data and H1, H2, H3. This will continue until the inter-
preter returns to NORM or CONC (pointer mover state
machine) states and a J1 byte is received.
NORM
CONC
AIS
2xCONC
2xNORM
2xNORM
2xAS
2 x CONC
2 x AIS
相關PDF資料 |
PDF描述 |
|---|---|
| ORT8850L | Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
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| OS1010 | Optoelectronic |
| OS1011 | SINGLE 1.8V, 200 KHZ OP, E TEMP, -40C to +125C, 8-PDIP, TUBE |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ORT8850H-1BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BMN680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-2BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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