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參數資料
| 型號： | ORT8850H |
| 英文描述： | Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| 中文描述： | 現場可編程系統(tǒng)芯片（促進文化基金）8通道x 850 Mbits /秒背板收發(fā)器 |
| 文件頁數： | 26/112頁 |
| 文件大?。?/td> | 2417K |
| 代理商： | ORT8850H |
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26
Agere Systems Inc.
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Backplane Transceiver Core Detailed Description
(continued)
SPE and C1J1 Outputs
. These two signals for each channel are passed to the FPGA logic to allow a pointer pro-
cessor or other function to extract payload without interpreting the pointers. For the ORT8850, each frame has
12 STS-1s. In the SPE region, there are 12 J1 pulses for each STS-1s. There is one C1(J0, new SONET specifica-
tions use J0 instead of C1 as section trace to identify each STS-1 in an STS-N) pulse in the TOH area for one
frame. Thus, there is a total of 12 J1 pulses and one C1(J0) pulse per frame. C1(J0) pulse is coincident with the J0
of STS1 #1. In each frame, the SPE flag is active when the data stream is in SPE area. SPE behavior is dependent
on pointer movement and concatenation. Note that in the TOH area, H3 can also carry valid data. When valid SPE
data is carried in this H3 slot, SPE is high in this particular TOH time slot. In the SPE region, if there is no valid data
during any SPE column, the SPE signal will be set to low. SPE allows a pointer processor to extract payload with-
out interpreting the pointers. The SPE and C1J1 functionality are described in Table 5. For generic data operation,
valid data is available when SPE is 1 and the C1J1 signal is ignored.
Table 5
.
SPE and C1J1 Functionality
Note:The following rules are observed for generating SPE and C1J1 signals: on occurrence of AIS-P on any of the STS-1, there is no corre-
sponding J1 pulse. In case of concatenated payloads (up to STS48c), only the head STS-1 of the group has an associated J1 pulse.
C1J1 signal tracks any pointer movements. During a negative justification event, SPE is set high during the H3 byte to indicate that pay-
load data is available. During a positive justification event, SPE is set low during the positive stuff opportunity byte to indicate that payload
data is not available.
5-9330(F)
Note:
C1J1 signal behavior shown in this figure is just for illustration purposes: C1 pulse position must always be as shown; however, position of J1
pulses vary based on path overhead location of each STS-1 within the STS-12 stream.
C1J1 signal must always be active during C1(J0) time slot of STS#1.
C1J1 signal must also be active during the twelve J1 time slots. However, C1J1 must not be active for any STS-1 for which AIS-P is generated.
Also, on concatenated payloads, only the head of the group must have a J1 pulse.
Figure 6. SPE and C1J1 Functionality
SPE
0
0
C1J1
0
1
Description
TOH information excluding C1(J0) of STS1 #1.
Position of C1(J0) of STS1 #1 (one per frame). Typically used to provide a
unique link identification (256 possible unique links) to help ensure cards
are connected into the backplane correctly or cables are connected
correctly.
SPE information excluding the 12 J1 bytes.
Position of the 12 J1 bytes.
1
1
0
1
STS-12
TOH ROW # 1
SPE ROW # 1
A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 J0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0
STS-12
SPE
C1J1
C1 PULSE
J1 PULSE OF
3RD STS-1
first SPE BYTES OF THE
12 STS-1S
1
2
3
4
5 6
7
8
9 10 11 12
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PDF描述 |
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相關代理商/技術參數 |
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| ORT8850H-1BM680C | 功能描述:FPGA - 現場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BM680I | 功能描述:FPGA - 現場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BMN680C | 功能描述:FPGA - 現場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BMN680I | 功能描述:FPGA - 現場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-2BM680C | 功能描述:FPGA - 現場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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