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| 型號： | ORLI10G1BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 7/78頁 |
| 文件大小： | 1689K |
| 代理商： | ORLI10G1BM680-DB |
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Lattice Semiconductor
ORCA ORLI10G Data Sheet
15
Transmit Path Details
In the transmit path, the ORLI10G embedded core can be broken down into three sections: the multiplexer, the
transmit side onboard PLLs, and the high-speed line interface. Note that both transmit and receive PLLs are in
addition to the four Programmable PLLs (PPLLs) in the FPGA portion of the ORLI10G.
MUX
The multiplexer takes data from the FPGA logic and multiplexes the data to rates for transfer by the highspeed line
interface. The multiplexer supports two modes of operation:
Multiplex-by-8
– The multiplexer converts the incoming 128 bits of data at 78 Mbits/s to 106 Mbits/s into 16 bits at 622 Mbits/s
to 850 Mbits/s. The incoming transmit reference clock is divided by 8 for connection to the internal FPGA
logic.
Multiplex-by-4
– The multiplexer converts the incoming 64 bits of data at 156 Mbits/s to 212 Mbits/s into 16 bits at 622 Mbits
to 850 Mbits/s. The transmit reference clock is divided by 4 for connection to the internal FPGA logic.
Onboard Transmit PLLs
The function of the onboard PLLs is to align the system data with the line data, which will be at a slightly higher rate
owing to the addition of the overhead bits. There are two PLLs on the transmit path. The input to the rst PLL,
TX1_PLL (see Figure 4), is the divided down transmit reference clock from the multiplexer. The TX1_PLL generates
a clock with a user-dened frequency ratio of M/N to the divided clock. This clock would generally be used to com-
pensate for different data rates due to overhead bits. M and N can be independently set from 1 to 40.
The TX2_PLL also takes its input reference from the divided down reference clock and is used to provide a bal-
anced divided clock across the FPGA-embedded core interface.
The TX2_PLL has a feedback path that compensates for routing delays to the embedded core/FPGA logic interface
for minimum clock skew.
In addition, the user can specify an additional skew on each clock in increments of 1/8 the clock period.
The selection of the MUX width (and corresponding clock division value), the TX1_PLL M and N values, and the
additional skew for TX1_PLL and TX2_PLL are specied by the user in a GUI interface provided in the ORLI10G
design kit.
A detailed block diagram of the transmit path in shown in Figure 4. Either TX1_VCOP, TX1_VCO, TX2_VCOP, or
TX2_VCO must be used to clock TX_DAT_IN[127:0] that is transmitted to the embedded block since this interface
must be frequency locked to the divided version of the referance clock. These PLLs can also be bypassed, where
the divided transmit reference clock is sent directly to the FPGA. TX_CLK8_IN[3:0] can be used to clock data trans-
mitted to the embedded block, but the preferred method is to use the internally generated clocks as described
above. If TX_CLK8_IN[3:0] are used, they must also be frequency locked to the reference clock and are thus also
required to be driven by TX1_VCOP, TX1_VCO, TX2_VCOP, or TX2_VCO.
Line Interface
In the transmit path, 16-bit data and associated clocks are outputs from the line interface. Typical data rates are
expected to range from 622 Mbits/s to 850 Mbits/s for most applications. The 16-bit LVDS output data bus is actu-
ally composed of four 4-bit data buses with one clock for each 4-bit data bus. On the transmit side, these clocks will
all be synchronized. The ORLI10G uses LVDS (Low-Voltage Differential Signaling) drivers/receivers, which are
intended to provide point-to-point connection between the ORLI10G and optical transceiver (MUX/deMUX) parts.
The LVDS drivers are hot-swap compatible and can connect to other vendor's LVDS I/O buffers. The LVDS drivers
are terminated with a 100 resistor to improve performance.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORLI10G-1BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-1BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-1BMN680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-2BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-2BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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