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參數(shù)資料
| 型號(hào)： | ORLI10G1BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 56/78頁 |
| 文件大?。?/td> | 1689K |
| 代理商： | ORLI10G1BM680-DB |
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Lattice Semiconductor
ORCA ORLI10G Data Sheet
6
timing requirement information through logical preferences only; thus, the designer is not required to have physical
knowledge of the implementation.
Following design entry, the development system's map, place, and route tools translate the netlist into a routed
FPGA. A oor planner is available for layout feedback and control. A static timing analysis tool is provided to deter-
mine design speed, and a back-annotated netlist can be created to allow simulation and timing.
Timing and simulation output les from ispLEVER are also compatible with many third-party analysis tools. A bit
stream generator is then used to generate the conguration data which is loaded into the FPGAs internal congu-
ration RAM, embedded block RAM, and/or FPSC memory.
When using the bit stream generator, the user selects options that affect the functionality of the FPGA. Combined
with the front-end tools, ispLEVER produces conguration data that implements the various logic and routing
options discussed in this data sheet.
FPSC Design Kit
Development is facilitated by an FPSC design kit which, together with ispLEVER software and third-party synthesis
and simulation engines, provides all software and documentation required to design and verify an FPSC implemen-
tation. Included in the kit are the FPSC conguration manager, Synopsys Smart Model
, and/or compiled Verilog
simulation model, HSPICE
and/or IBIS models for I/O buffers, and complete online documentation. The kit's soft-
ware couples with ispLEVER software, providing a seamless FPSC design environment. More information can be
obtained by visiting the Lattice website at www.latticesemi.com or contacting a local sales ofce.
FPGA Logic Overview
The ORCA Series 4 architecture is a new generation of SRAM-based programmable devices from Lattice. It
includes enhancements and innovations geared toward today's high-speed systems on a single chip. Designed
with networking applications in mind, the Series 4 family incorporates system-level features that can further reduce
logic requirements and increase system speed. ORCA Series 4 devices contain many new patented enhance-
ments and are offered in a variety of packages and speed grades.
The hierarchical architecture of the logic, clocks, routing, RAM, and system-level blocks create a seamless merge
of FPGA and ASIC designs. Modular hardware and software technologies enable System-on-a-Chip integration
with true plug-and-play design implementation.
The architecture consists of four basic elements: Programmable Logic Cells (PLCs), Programmable I/O cells
(PIOs), Embedded Block RAMs (EBRs), and system level features. These elements are interconnected with a rich
routing fabric of both global and local wires. An array of PLCs are surrounded by common interface blocks which
provide an abundant interface to the adjacent PLCs or system blocks. Routing congestion around these critical
blocks is eliminated by the use of the same routing fabric implemented within the programmable logic core. Each
PLC contains a PFU, (Supplementary Logic Interconnect) SLIC, local routing resources, and conguration RAM.
Most of the FPGA logic is performed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be per-
formed in the SLIC. The PIOs provide device inputs and outputs and can be used to register signals and to perform
input demultiplexing, output multiplexing, uplink and downlink functions, and other functions on two output signals.
Large blocks of 512 x 18 quadport RAM complement the existing distributed PFU memory. The RAM blocks can be
used to implement RAM, ROM, FIFO, multiplier, and CAM. Some of the other system-level functions include the
MPI, PLLs, and the Embedded System Bus (ESB).
PLC Logic
Each PFU within a PLC contains eight 4-input (16-bit) LUTs, eight latches/Flip-Flops, and one additional Flip-Flop
that may be used independently or with arithmetic functions.
The PFU is organized in a twin-quad fashion; two sets of four LUTs and Flip-Flops that can be controlled indepen-
dently. Each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects.
LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit
modes. The carry-out of either mode may be registered in the ninth Flip-Flop for pipelining. Each PFU may also be
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORLI10G-1BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-1BMN680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-1BMN680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-2BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-2BM680I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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