參數(shù)資料
型號(hào)： ORLI10G1BM680-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝： PLASTIC, FBGA-680
文件頁(yè)數(shù)： 16/78頁(yè)
文件大?。?/td> 1689K
代理商： ORLI10G1BM680-DB
Lattice Semiconductor
ORCA ORLI10G Data Sheet
23
ORLI10G Multiplexer (Tx) Detail
The multiplexer module converts the incoming 128 bits of data from the FPGA logic at 78 MHz/106 MHz or
64 bits of data from the FPGA logic at 156 MHz/212 MHz into 16 bits of data at 622 MHz/850 MHz. It has been
implemented as two stages. The rst stage deinterleaves each incoming byte into a different byte stream that can
be serially output on the output data pins. The second stage outputs these bytes into 16 bits or four groups of 4 bits,
depending upon the mode of operation. Functionally, the multiplexer architecture consists of three blocks: the par-
allel-to-serial conversion, the counters, and the deinterleaving.
Two options are available for the transmit clocks. The clock signals TX_CLK_IN[3:0] can be used to transfer data to
the internal core or an internal clock can be used. The preferred method is to use the internal clock. Two options
are also available for the enable signals. The enable signals TX_ENB8_IN[3:0] can be used or they can be gener-
ated internally. The preferred method is to use the internal enables.
For divide-by-8 mode, the rst stage of the line interface module deinterleaves each incoming byte of data into a
different byte stream on the 78 MHz/106 MHz (TX_CLK8_IN[3:0] or internal) clock. This data is then registered on
the rising edge of the 622 MHz/850 MHz (TX_CLK_IN) clock at the falling edge of the 78 MHz/106 MHz clock. The
enable inputs (TX_ENB8_IN[3:0] or internal) are used to transfer data from the low-speed clock to the high-speed
clock, as well as synchronizing the counters of parallel-to-serial conversion which are running at the high-speed
clock. Generally, these enables are generated in the embedded core and the TX_ENB8_IN[3:0] signals to the
embedded core are not used.
For divide-by-4 mode, the rst stage of the line interface module deinterleaves each incoming byte of data into a
different byte stream on the 156 MHz/212 MHz (TX_CLK8_IN[3:0] or internal) clock. This data is then registered on
the rising edge of the 622 MHz/850 MHz (TX_CLK_IN) clock at the falling edge of the 156 MHz/212 MHz clock.
The enable inputs (TX_ENB8_IN[3:0] or internal) are used to transfer data from the low-speed clock to the high-
speed clock, as well as synchronizing the counters of parallel-to-serial conversion which are running at the high-
speed clock. Again, both TX_CLK8_IN[3:0] and TX_ENB8_IN[3:0] are not generally used.
The enable inputs (TX_ENB8_IN[3:0]) are required to be four (divide by 4) or eight (divide by 8) TX_CLK_IN clock
cycles wide. If they are used, they have to be synchronous to their corresponding TX_CLK8_IN[3:0] clock. Each of
these four TX_CLK8_IN[3:0] clocks must also be frequency locked to the TX_CLK_IN signal.
The TX_CLK_OUT[3:0] clock outputs from the ORLI10G are provided for transferring each 4 bits of data per clock.
All data to be transmitted to the embedded core must be frequency locked to the TX_CLK_IN signal. Thus, the
divided version of this clock found at the embedded core interface should always be used to transfer data from the
FPGA logic to the embedded core. These clock signals are available from the TX PLL outputs (TX1_VCO,
TX1_VCOP, TX2_VCO, TX2_VCOP). Figure 11 shows the valid data input bits to the multiplexer in each of the four
modes (divide-by-8 and divide-by-4 modes). Figure 12— Figure 15 show the multiplexer input transmit reference
clock, data, enable, and clock waveforms and output clock and data waveforms for all four modes.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORLI10G-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-1BMN680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORLI10G-2BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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