
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
REV 1.1 June, 2000
32
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Burst Stop Command
Once a burst read or write operation has been initiated, there exist several methods in which to terminate the burst operation prematurely.
These methods include using another Read or Write Command to interrupt an existing burst operation or using a Precharge Command to
interrupt a burst cycle and close the active bank. When interrupting a burst with another Read or Write Command care must be taken to
avoid DQ contention.
If the burst length is full page, the Burst Stop Command may also be used to terminate the existing burst operation but leave the bank open
for future Read or Write Commands to the same page of the active bank. Use of the Burst Stop Command during other burst length
operations is illegal. The Burst Stop Command is defined by having /RAS and /CAS high with /CS and /WE low at the rising edge of the
clock.
When using the Burst Stop Command during a burst read cycle, the data DQs go to a high impedance state after a delay which is equal to
the /CAS Latency set in the Mode Register.
Termination of a Burst Read Operation
CLK
COMMAND
T0
T1
T2
T3
T4
T5
T6
T7
READ A
NOP
Burst Length = Full Page, CAS Latency = 2, 3
T8
Burst
Stop
CAS latency = 2
tCK2, DQs
CAS latency = 3
tCK3, DQs
DOUT A0
DOUT A1
DOUT A2
DOUT A0
DOUT A1
DOUT A2
DOUT A3
The burst ends after a delay equal to the
CAS latency.
If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored.
Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory.
Termination of a Burst Write Operation
CLK
COMMAND
T0
T1
T2
T3
T4
T5
T6
T7
NOP
WRITE A
NOP
Burst Length = Full Page, CAS Latency = 2, 3
T8
Burst
Stop
CAS latency=2,3
DQs
DIN A0
DIN A1
DIN A2
don't care
Input data for the Write is masked