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參數(shù)資料
| 型號： | NT56V6620C0T-75 |
| 廠商： | NANYA TECHNOLOGY CORP |
| 元件分類： | DRAM |
| 英文描述： | SYNCHRONOUS DRAM, PDSO54 |
| 封裝： | 0.400 INCH, SSOP2-54 |
| 文件頁數(shù)： | 21/66頁 |
| 文件大?。?/td> | 1701K |
| 代理商： | NT56V6620C0T-75 |
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
REV 1.1 June, 2000
28
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Burst Read Command
The Burst Read command is initiated by having /CS and /CAS low while holding /RAS and /WE high at the rising edge of the clock. The
address inputs determine the starting column address for the burst. The Mode Register sets the type of burst (sequential or interleave) and
the burst length (1, 2, 4, 8, full page). The delay from the start of the command to when the data from the first cell appears on the outputs is
equal to the value of the /CAS latency that is set in the Mode Register.
Burst Read Operation
CLK
COMMAND
T0
T1
T2
T3
T4
T5
T6
T7
READ A
NOP
Burst Length = 4, CAS Latency = 2, 3
T8
NOP
CAS latency = 2
tCK2, DQs
CAS latency = 3
tCK3, DQs
DOU A0
DOU A1
DOU A2
DOU A3
DOU A0
DOU A1
DOU A2
DOU A3
Read Interrupted by a Read
A Burst Read may be interrupted before completion of the burst by another Read Command, with the only restriction being that the interval
that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are
overridden by the new address with the full burst length. The data from the first Read Command continues to appear on the outputs until the
/CAS latency from the interrupting Read Command is satisfied, at this point the data from the interrupting Read Command appears.
Read Interrupted by a Read
CLK
COMMAND
T0
T1
T2
T3
T4
T5
T6
T7
READ A
READ B
NOP
Burst Length = 4, CAS Latency = 2, 3
T8
NOP
CAS latency = 2
tCK2, DQs
CAS latency = 3
tCK3, DQs
DOU A0
DOU B0
DOU B1
DOU B2
DOU A0
DOU B0
DOU B1
DOU B2
DOU B3
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