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參數(shù)資料
| 型號： | NT56V6620C0T-75 |
| 廠商： | NANYA TECHNOLOGY CORP |
| 元件分類： | DRAM |
| 英文描述： | SYNCHRONOUS DRAM, PDSO54 |
| 封裝： | 0.400 INCH, SSOP2-54 |
| 文件頁數(shù)： | 25/66頁 |
| 文件大?。?/td> | 1701K |
| 代理商： | NT56V6620C0T-75 |
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
REV 1.1 June, 2000
31
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is registered. The DQs must be in
the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data contention. When the
Read Command is registered, any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the
Read Command is initiated will actually be written to the memory.
Minimum Write to Read Interval
CLK
COMMAND
T0
T1
T2
T3
T4
T5
T6
T7
WRITE A
READ B
NOP
Burst Length = 4, CAS Latency = 2, 3
T8
NOP
CAS latency = 2
tCK2, DQs
CAS latency = 3
tCK3, DQs
DOU B0
DOU B1
DOU B2
DOU B3
DIN A0
don't care
DIN A0
don't care
DOU B0
DOU B1
DOU B2
DOU B3
Input data for the write is masked
don't care
Input data must be removed from the DQs at least one clock cycle
before the data appears on the outputs to avoid data contention.
Non-Minimum Write to Read Interval
CLK
COMMAND
T0
T1
T2
T3
T4
T5
T6
T7
WRITE A
NOP
READ B
NOP
Burst Length = 4, CAS Latency = 2, 3
T8
NOP
CAS latency = 2
tCK2, DQs
CAS latency = 3
tCK3, DQs
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DIN A0
DIN A1
DIN A0
DOUT B0
DOUT B1
DOUT B2
Input data for the write is masked
don't care
Input data must be removed from the DQs at least one clock cycle
before the data appears on the outputs to avoid data contention.
don't care
DIN A1
don't care
DOUT B3
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