參數資料
型號: NRF9E5-EVKIT433
廠商: Electronic Theatre Controls, Inc.
英文描述: 433/868/915MHz RF Transceiver with Embedded 8051 Compatible Microcontroller and 4 Input, 10 Bit ADC
中文描述: 433/868/915MHz RF收發(fā)器與8051兼容的嵌入式微控制器和4輸入,10位ADC
文件頁數: 87/104頁
文件大?。?/td> 1436K
代理商: NRF9E5-EVKIT433
PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway -Phone +4772898900 - Fax +4772898989
Revision: 1.1
Page 87 of 104
June 2004
For noise rejection, the serial port establishes the content of each received bit by a
majority decision of three consecutive samples in the middle of each bit time. This is
especially true for the start bit. If the falling edge on rxd_in is not verified by a majority
decision of three consecutive samples (low), then the serial port stops reception and
waits for another falling edge on rxd_in.
At the middle of the stop bit time, the serial port checks for the following conditions:
-
RI = 0
- If SM2 = 1, the state of the stop bit is 1
(if SM2 = 0, the state of the stop bit does not matter)
If the above conditions are met, the serial port then writes the received byte to the SBUF
register, loads the stop bit into RB8, and sets the RI bit. If the above conditions are not
met, the received data is lost, the SBUF register and RB8 bit are not loaded, and the RI
bit is not set. After the middle of the stop bit time, the serial port waits for another high-
to-low transition on the rxd_in pin.
Mode 1 operation is identical to that of the standard 8051 when Timers 1 and 2 use
CPU_clk/12 (the default).
18.9.3
Mode 2
Mode 2 provides asynchronous, full-duplex communication, using a total of eleven bits:
- One start bit
- Eight data bits
- One programmable 9th bit
- One stop bit
The data bits are transmitted and received LSB first. For transmission, the 9th bit is
determined by the value in TB8. To use the 9th bit as a parity bit, move the value of the
P bit (SFR PSW.0) to TB8.
The mode 2 baud rate is either CPU_clk/32 or CPU_clk/64, as determined by the SMOD
bit. The formula for the mode 2 baud rate is:
Baud Rate =
64
2
clk
SMOD
Mode 2 operation is identical to the standard 8051.
18.9.3.1
Mode 2 Transmit
Figure 30 illustrates the mode 2 transmit timing. Transmission begins after the first
rollover of the divide-by-16 counter following a software write to SBUF . The UART
shifts data out on the txd pin in the following order: start bit, data bits (LSB first), 9th
bit, stop bit. The TI bit is set when the stop bit is placed on the txd pin.
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