參數(shù)資料
型號(hào)： NRF9E5-EVKIT433
廠商： Electronic Theatre Controls, Inc.
英文描述： 433/868/915MHz RF Transceiver with Embedded 8051 Compatible Microcontroller and 4 Input, 10 Bit ADC
中文描述： 433/868/915MHz RF收發(fā)器與8051兼容的嵌入式微控制器和4輸入，10位ADC
文件頁(yè)數(shù)： 48/104頁(yè)
文件大?。?/td> 1436K
代理商： NRF9E5-EVKIT433
PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway -Phone +4772898900 - Fax +4772898989
Revision: 1.1
Page 48 of 104
June 2004
Table 42 explains the bit functions of the EIP register.
Bit
EIP.7-5
EIP.4
Function
Reserved. Read as 1.
PWDI - Wakeup interrupt priority control. WDPI = 0 sets the wakeup interrupt (wdti)
to low priority. PS = 1 sets wakeup timer interrupt to high priority.
PX5 - interrupt 5 priority control. PX5 = 0 sets interrupt 5 (radio AM) to low priority.
PX5 = 1 sets interrupt 5 to high priority.
PX4 - interrupt 4 priority control. PX4 = 0 sets interrupt 4 (radio DR) to low priority.
PX4 = 1 sets interrupt 4 to high priority.
PX3 - interrupt 3 priority control. PX3 = 0 sets interrupt 3 (SPI READY) to low
priority. PX3 = 1 sets interrupt 3 to high priority.
PX2 - interrupt 2 priority control. PX2 = 0 sets interrupt 2 (ADC EOC) to low priority.
PX2 = 1 sets interrupt 2 to high priority.
EIP.3
EIP.2
EIP.1
EIP.0
Table 42 EIP Register – SFR 0xF8.
15.2
Interrupt Processing
When an enabled interrupt occurs, the CPU vectors to the address of the interrupt
service routine (ISR) associated with that interrupt, as listed in Table 36. The CPU
executes the ISR to completion unless another interrupt of higher priority occurs. Each
ISR ends with an RETI (return from interrupt) instruction. After executing the RETI, the
CPU returns to the next instruction that would have been executed if the interrupt had
not occurred.
An ISR can only be interrupted by a higher priority interrupt. That is, an ISR for a low-
level interrupt can be interrupted only by a high-level interrupt. The CPU always
completes the instruction in progress before servicing an interrupt. If the instruction in
progress is RETI, or a write access to any of the IP, IE, EIP, or EIE SFRs, the CPU
completes one additional instruction before servicing the interrupt.
15.3
Interrupt Masking
The EA bit in the IE SFR (IE.7) is a global enable for all interrupts. When EA = 1, each
interrupt is enabled/masked by its individual enable bit. When EA = 0, all interrupts are
masked. Table 36 provides a summary of interrupt sources, flags, enables, and priorities.
15.4
Interrupt Priorities
There are two stages of interrupt priority assignment: interrupt level and natural priority.
The interrupt level (high, or low) takes precedence over natural priority. All interrupts
can be assigned either high or low priority. In addition to an assigned priority level (high
or low), each interrupt has a natural priority, as listed in Table 36. Simultaneous
interrupts with the same priority level (for example, both high) are resolved according to
their natural priority. For example, if INT0_N and int2 are both programmed as high
priority, INT0_N takes precedence. Once an interrupt is being serviced, only an interrupt
of higher priority level can interrupt the service routine of the interrupt currently being
serviced.
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