參數(shù)資料
型號(hào): NRF9E5-EVKIT433
廠商: Electronic Theatre Controls, Inc.
英文描述: 433/868/915MHz RF Transceiver with Embedded 8051 Compatible Microcontroller and 4 Input, 10 Bit ADC
中文描述: 433/868/915MHz RF收發(fā)器與8051兼容的嵌入式微控制器和4輸入,10位ADC
文件頁數(shù): 38/104頁
文件大?。?/td> 1436K
代理商: NRF9E5-EVKIT433
PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway -Phone +4772898900 - Fax +4772898989
Revision: 1.1
Page 38 of 104
June 2004
11.5
ADC - Configuration Register Description
Parameter
Bitwidth
CSTARTN
1
Description
Positive edge of this signal will start one AD conversion when ADCRUN is
inactive. This bit is internally synchronized to the ADC clock
ADC running continuously when active.
CSTARTN is ignored in this case
Enable ADC
ADCRUN
1
ADC_PWR_
UP
VFSSEL
1
1
Select reference for AD converter
0: Use internal band gap reference (nominally 1.22V)
1: Use external pin AREF for reference (ignored if CHSEL=[1xxx]).
Cannel select input
0000: AIN0
0001: AIN1
0010: AIN2
0011: AIN3
1xxx: internal VDD/3.
Set A/D converter resolution:
00: 6 bit
01: 8 bit
10: 10 bit
11: 12 bit
Enable differential measurements, AIN0 must be used as inverting input and one of
the other inputs AIN1 to AIN3, as selected by ADCSEL, must be used as
noninverting input.
Select left or right justified data format:
0: Data will be left justified in ADC_DATA_REG
1: Data will be right justified in ADC_DATA_REG
Table 23 ADC Configuration-register description.
CHSEL
4
RESCTRL
2
DIFFMODE,
1
ADC_
RL_JUST
1
11.6
Status-Register Description
Parameter
Bitwidth
AM
Description
Address Match, indicate that the receiver has received an address equal to its own
identity.
Detailed description in chapter 9.8.
Carrier Detect, indicates that a carrier is found on the receiving channel. Detailed
description in chapter 9.7
Data Ready, indicate that the receiver has received a data package with correct
address and CRC. Detailed description in chapter 9.9.
End Of Conversion, indicates that an AD conversion is completed and that data is
placed in ADC_DATA_REG.
Overflow indication in ADC
RFLAG[2]: Underflow (ADCDATA = 0)
RFLAG[1]: Overflow (ADCDATA = 2
N
-1)
RFLAG[0]: Over range = RFLAG[1] or RFLAG[2]
1
CD
1
DR
1
EOC
1
ADC_
RFLAG
3
Table 24 Status-register description.
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