參數(shù)資料
型號： NRF9E5-EVKIT433
廠商： Electronic Theatre Controls, Inc.
英文描述： 433/868/915MHz RF Transceiver with Embedded 8051 Compatible Microcontroller and 4 Input, 10 Bit ADC
中文描述： 433/868/915MHz RF收發(fā)器與8051兼容的嵌入式微控制器和4輸入，10位ADC
文件頁數(shù)： 85/104頁
文件大小： 1436K
代理商： NRF9E5-EVKIT433
PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway -Phone +4772898900 - Fax +4772898989
Revision: 1.1
Page 85 of 104
June 2004
Desired
Baud Rate
SMOD
C/T
Timer 1
Mode
TH1
for 16 MHz
CPU clk
0xF3
0xE6
0XcC
0x98
0x30
Value
TH1
for 8 MHz
CPU clk
-
0xF3
0xE6
0xCC
0x98
Value
19.2 Kb/s
9.6 Kb/s
4.8 Kb/s
0.4 Kb/s
1.2 Kb/s
1
1
1
1
1
0
0
0
0
0
2
2
2
2
2
Table 72 Timer 1 Reload Values for Serial Port Mode 1 Baud Rates.
To use Timer 2 as the baud-rate generator, configure Timer 2 in auto-reload mode and
set the TCLK and/or RCLK bits in the T2CON SFR. TCLK selects Timer 2 as the baud-
rate generator for the transmitter; RCLK selects Timer 2 as the baud-rate generator for
the receiver. The 16-bit reload value for Timer 2 is stored in the RCAP2L and RCA2H
SFRs, which makes the equation for the Timer 2 baud rate:
Baud Rate =
RCAP2L})
{RCAP2H,
(65536
x
32
clk
where RCAP2H,RCAP2L is the content of RCAP2H and RCAP2L taken as a 16-bit
unsigned number. The 32 in the denominator is the result of the CPU_clk signal being
divided by 2 and the Timer 2 overflow being divided by 16. Setting TCLK or RCLK to
1 automatically causes the CPU_clk signal to be divided by 2, as shown in Figure 23
Timer 2 – Baud Rate Generator Mode, instead of the 4 or 12 determined by the T2M bit
in the CKCON SFR.
To derive the required RCAP2H and RCAP2L values from a known baud rate, use the
equation:
RCAP2H,RCAP2L = 65536 –
Rate
Baud
x
32
clk
Table
Table 73
lists sample values of RCAP2L and RCAP2H for a variety of
desired baud rates.
16 MHz CPU clk
Baud Rate
C/T
2
RCAP2H
57.6 Kb/s
0
0xFF
19.2 Kb/s
0
0xFF
9.6 Kb/s
0
0xFF
4.8 Kb/s
0
0xFF
0.4 Kb/s
0
0xFF
1.2 Kb/s
0
0xFE
RCAP2L
0xF7
0xE6
0xCC
0x98
0x30
0x5F
Table 73 Timer 2 Reload Values for Serial Port Mode 1 Baud Rates.
When either RCLK or TCLK is set, the TF2 flag will not be set on a Timer 2
rollover, and the t2ex reload trigger is disabled.
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相關代理商/技術參數(shù)
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