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參數(shù)資料
| 型號： | NCP1611BDR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 27/29頁 |
| 文件大小： | 879K |
| 描述： | IC PFC CTLR HE ENHANCED 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 系列： | * |
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NCP1611
http://onsemi.com
27
gradual decrease of V
CONTROL
avoids a line current
discontinuity and limits the risk of false triggering.
Pin2 is also used to sense the line for feedforward. A similar
method is used:
The V
SENSE
pin voltage is compared to a 2.2 V
reference.
If V
pin2
exceeds 2.2 V, the circuit detects a highline
condition and the loop gain is divided by three (the
internal PWM ramp slope is three times steeper)
Once this occurs, if V
pin2
remains below 1.7 V for
25 ms, the circuit detects a lowline situation
(500 mV hysteresis).
At startup, the circuit is in lowline state ( LLine high )
until V
pin2
exceeds 2.2 V.
The line range detection circuit allows more optimal loop
gain control for universal (wide input mains) applications.
As portrayed in Figure 69, the pin 2 voltage is also utilized
to generate the current information required for the
frequency foldback function.
Figure 69. Input Line Sense Monitoring
Vsense pin
Thermal Shutdown (TSD)
An internal thermal circuitry disables the circuit gate drive
and keeps the power switch off when the junction
temperature exceeds 150癈. The output stage is then
enabled once the temperature drops below about 100癈
(50癈 hysteresis).
Output Drive Section
The output stage contains a totem pole optimized to
minimize the cross conduction current during high
frequency operation. The gate drive is kept in a sinking
mode whenever the UnderVoltage Lockout is active or
more generally whenever the circuit is off (i.e., when the
Fault Latch of the block diagram is high). Its high current
capability (500 mA/+800 mA) allows it to effectively drive
high gate charge power MOSFET. As the circuit exhibits a
large V
CC
range (up to 35 V), the drive pin voltage is clamped
not to provide the MOSFET gate with more than 14 V.
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