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參數(shù)資料
| 型號： | NCP1611BDR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 21/29頁 |
| 文件大?。?/td> | 879K |
| 描述： | IC PFC CTLR HE ENHANCED 8-SOIC |
| 標準包裝： | 3,000 |
| 系列： | * |
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NCP1611
http://onsemi.com
21
BO pin
V to I
converter
Vcontrol pin
V to I
converter
Multiplier
FFcontrol pin
SUM
RAMP
1V
skip2
pfcOK
I
BO
I
REGUL
I
BO
I
REGUL
K
m
. I
REGUL
. I
BO
I
REGUL
= K .V
REGUL
R
FF
+
LLine
V
SENSE
pin
V
CONTROL
pin
FFcontrol pin
0.75 V / 0.65 V
SKIP
RAMP
SUM
pfcOK
Figure 61. Generation of the Current Information
Skip Mode
As illustrated in Figure 61, the circuit also skips cycles
near the line zero crossing where the current is very low. A
comparator monitors the pin 3 voltage ( FFcontrol
voltage) and inhibits the drive when V
pin3
is lower than a
0.65 V internal reference. Switching resumes when V
pin3
exceeds 0.75 V (0.1 V hysteresis). This inhibits circuit
operation when the power transfer is particularly inefficient
at the expense of slightly increased current distortion. When
superior power factor is needed, this function can be
inhibited offsetting the FFcontrol pin by 0.75 V. The skip
mode capability is disabled whenever the PFC stage is not
in nominal operation (as dictated by the pfcOK signal
see block diagram and pfcOK Internal Signal Section).
The circuit does not abruptly interrupt the switching when
V
pin3
goes below 0.65 V. Instead, the signal V
TON
that
controls the ontime is gradually decreased by grounding
the V
REGUL
signal applied to the V
TON
processing block (see
Figure 9). Doing so, the ontime smoothly decays to zero in
three to four switching periods typically. Figure 62 shows
the practical implementation.
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