參數(shù)資料
型號: NCP1611BDR2G
廠商: ON Semiconductor
文件頁數(shù): 26/29頁
文件大?。?/td> 879K
描述: IC PFC CTLR HE ENHANCED 8-SOIC
標(biāo)準(zhǔn)包裝: 3,000
系列: *
NCP1611
http://onsemi.com
26
OCP signal turns high to reset the PWM latch and forces the
driver low. A 200 ns blanking time prevents the OCP
comparator from tripping because of the switching spikes
that occur when the MOSFET turns on.
The CS pin is also designed to receive a signal from an
auxiliary winding for Zero Current Detection. As illustrated
in Figure 68, an internal ZCD comparator monitors the pin4
voltage   and   if   this   voltage   exceeds   750   mV,   a
demagnetization phase is detected (signal ZCD is high). The
auxiliary winding voltage is applied thought a diode to
prevent this signal from distorting the current sense
information during the ontime. Thus, the OCP protection
is not impacted by the ZCD sensing circuitry. This
comparator incorporates a 500 mV hysteresis and is able to
detect ZCD pulses longer than 200 ns. When pin4 voltage
drops below the lower ZCD threshold, the driver can turn
high within 200 ns.
It may happen that the MOSFET turns on while a huge
current flows through the inductor. As an example such a
situation can occur at startup when large inrush currents
charge the bulk capacitor to the line peak voltage.
Traditionally, a bypass diode is generally placed between the
input and output highvoltage rails to divert this inrush
current. If this diode is accidently shorted, the MOSFET will
also see a high current when it turns on. In both cases, the
current can be large enough to trigger the ZCD comparator.
An AND gate detects that this event occurs while the drive
signal is high. In this case, the OverStress signal goes high
and disables the driver for an 800 ms delay. This long delay
leads to a very low dutyratio operation in case of
OverStress fault in order to limit the risk of overheating.
When no signal is received that triggers the ZCD
comparator during the offtime, an internal 200ms
watchdog timer initiates the next drive pulse. At the end of
this delay, the circuit senses the CS/ZCD pin impedance to
detect a possible grounding of this pin and prevent
operation. The CS/ZCD external components must be
selected to avoid false fault detection. 3.9 kW is the
recommended minimum impedance to be applied to the
CS/ZCD pin when considering the NCP1611 parameters
tolerance over the 40癈 to 125癈 temperature range.
Practically, R
cs
  must be higher than 3.9 kW in the
application of Figure 68.
Figure 68. Current Sense and Zero Current Detection Blocks
BrownOut Detection
The V
SENSE
  pin (pin2) receives a portion of the
instantaneous input voltage (V
in
). As V
in
  is a rectified
sinusoid, the monitored signal varies between zero or a small
voltage and a peak value.
For the brownout block, we need to ensure that the line
magnitude is high enough for operation. This is done as
follows:
 The V
SENSE
 pin voltage is compared to a 1 V
reference.
 If V
pin2
 exceeds 1 V, the input voltage is considered
sufficient
 If V
pin2
 remains below 0.9 V for 50 ms, the circuit
detects a brownout situation (100 mV hysteresis).
By default, when the circuit starts operation, the circuit is
in a fault state (BO_NOK high) until V
pin2
 exceeds 1 V.
When BO_NOK is high, the drive is not disabled.
Instead, a 50 mA current source is applied to pin 1 to
gradually reduce V
CONTROL
. As a result, the circuit only
stops pulsing when the staticOVP function is activated (that
is when V
CONTROL
 reaches the skip detection threshold). At
that moment, the circuit turns off (see Figure 2). This
method limits any risk of false triggering. The input of the
PFC stage has some impedance that leads to some sag of the
input voltage when the input current is large. If the PFC stage
suddenly stops while a high current is drawn from the mains,
the abrupt decay of the current may make the input voltage
rise and the circuit detect a correct line level. Instead, the
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