參數(shù)資料
型號： NCP1611BDR2G
廠商： ON Semiconductor
文件頁數(shù)： 23/29頁
文件大?。?/td> 879K
描述： IC PFC CTLR HE ENHANCED 8-SOIC
標準包裝： 3,000
系列： *
NCP1611
http://onsemi.com
23
In some cases, the system enters then the deadtime (t
3
) that
lasts until the next clock is generated.
One can show that the ac line current is given by:
I
in
+ V
in
t
1
t
1
) t
2
2TL
(eq. 1)
Where T = (t
1
 + t
2
 + t
3
) is the switching period and V
in
 is
the ac line rectified voltage.
In light of this equation, we immediately note that I
in
 is
proportional to V
in
 if [t
1
 (t
1
 + t
2
) / T] is a constant.
Figure 64. PFC Boost Converter (left) and Inductor Current in DCM (right)
The NCP1611 operates in voltage mode. As portrayed by
Figure 8, the MOSFET ontime t
1
 is controlled by the signal
V
ton
 generated by the regulation block and an internal ramp
as follows:
t
1
+
C
ramp
@ V
ton
I
ch
(eq. 2)
The charge current is constant at a given input voltage (as
mentioned, it is 3 times higher at high line compared to its
value at low line). C
ramp
 is an internal capacitor.
The output of the regulation block (V
CONTROL
) is linearly
transformed into a signal (V
REGUL
) varying between 0 and
1 V. (V
REGUL
) is the voltage that is injected into the PWM
section to modulate the MOSFET dutycycle. The
NCP1611 includes some circuitry that processes (V
REGUL
)
to form the signal (V
ton
) that is used in the PWM section (see
Figure 9). (V
ton
) is modulated in response to the deadtime
sensed during the precedent current cycles, that is, for a
proper shaping of the ac line current. This modulation leads
to:
V
ton
+
T @ V
REGUL
t
1
) t
2
(eq. 3)
or
V
ton
@
t
1
) t
2
T
+ V
REGUL
Given the low regulation bandwidth of the PFC systems,
(V
CONTROL
) and then (V
REGUL
) are slow varying signals.
Hence, the (V
ton
 " (t
1
 + t
2
) / T) term is substantially constant.
Provided that in addition, (t
1
) is proportional to (V
ton
),
Equation 1 leads to: (I
in
 = k " V
in
), where k is a constant.
More exactly:
I
in
+ k @ V
in
where :  k + constant +
1
2L
@
V
REGUL
V
REGUL
max
@ t
on,max
Where t
on
,
max
 is the maximum ontime obtained when
V
REGUL
  is at its (V
REGUL
)
max
  maximum level. The
parametric table shows that t
on
,
max
  is equal to 25 ms
(T
ON(LL)
) at low line and to 8.3 ms (T
ON(HL)
) at high line
(when pin2 happens to exceed 2.2 V with a pace higher than
40 Hz  see BO 25 ms blanking time).
The input current is then proportional to the input voltage.
Hence, the ac line current is properly shaped.
One can note that this analysis is also valid in the CrM
case. This condition is just a particular case of this
functioning where (t
3
=0), which leads to (t
1
+t
2
=T) and
(V
TON
=V
REGUL
). That is why the NCP1611 automatically
adapts to the conditions and transitions from DCM and CrM
(and vice versa) without power factor degradation and
without discontinuity in the power delivery.
Hence, we can rewrite the above equation as follows:
I
in
+
V
in
@ T
ON(LL)
2 @ L
@
V
REGUL
V
REGUL
max
at low line.
I
in
+
V
in
@ T
ON(HL)
2 @ L
@
V
REGUL
V
REGUL
max
at high line.
From these equations, we can deduce the expression of the
average input power:
P
in,avg
+
V
in,rms
2
@ V
REGUL
@ T
ON(LL)
2 @ L @
V
REGUL
max
at low line
P
in,avg
+
V
in,rms
2
@ V
REGUL
@ T
ON(HL)
2 @ L @
V
REGUL
max
at high line
Where (V
REGUL
)
max
 is the 1 V V
REGUL
 maximum value.
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