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參數(shù)資料
| 型號(hào)： | NCP1611BDR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 19/29頁 |
| 文件大?。?/td> | 879K |
| 描述： | IC PFC CTLR HE ENHANCED 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 系列： | * |
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NCP1611
http://onsemi.com
19
Maximum Current Limit: the circuit senses the
MOSFET current and turns off the power switch if
the set current limit is exceeded. In addition, the
circuit enters a low dutycycle operation mode when
the current reaches 150% of the current limit as a
result of the inductor saturation or a short of the
bypass diode.
UnderV oltage Protection: this circuit turns off when
it detects that the output voltage is below 12% of the
voltage reference (typically). This feature protects
the PFC stage if the ac line is too low or if there is a
failure in the feedback network (e.g., bad
connection).
BrownOut Detection: the circuit detects low ac line
conditions and stops operation thus protecting the
PFC stage from excessive stress.
Thermal Shutdown: an internal thermal circuitry
disables the gate drive when the junction
temperature exceeds 150癈 (typically). The circuit
resumes operation once the temperature drops below
approximately 100癈 (50癈 hysteresis).
" Output Stage Totem Pole: the NCP1611 incorporates a
0.5 A / +0.8 A gate driver to efficiently drive most
TO220 or TO247 power MOSFETs.
NCP1611 Operation Modes
As mentioned, the NCP1611 PFC controller implements
a Current Controlled Frequency Foldback (CCFF) where:
The circuit operates in classical Critical conduction
Mode (CrM) when the inductor current exceeds a
programmable value.
When the current is below this preset level, the
NCP1611 linearly reduces the operating frequency
down to about 20 kHz when the current is zero.
High Current
No delay
?/DIV>
CrM
Low Current
The next cycle is
delayed
Lower Current
Longer dead time
Timer delay
Timer delay
High Current
No delay
?/DIV>
CrM
Low Current
The next cycle is
delayed
Lower Current
Longer dead time
Timer delay
Timer delay
Figure 59. CCFF Operation
As illustrated in Figure 59, under high load conditions, the
boost stage is operating in CrM but as the load is reduced, the
controller enters controlled frequency discontinuous
operation.
Figure 60 details the operation. A voltage representative
of the input current ( current information ) is generated. If
this signal is higher than a 2.5 V internal reference (named
DeadTime Ramp Threshold in Figure 60), there is no
deadtime and the circuit operates in CrM. If the current
information is lower than the 2.5 V threshold, a deadtime
is inserted that lasts for the time necessary for the internal
ramp to reach 2.5 V from the current information floor.
Hence, the lower the current information is, the longer the
deadtime. When the current information is 0.75 V, the
deadtime is approximately 45 ms.
To further reduce the losses, the MOSFET turns on is
stretched until its drainsource voltage is at its valley. As
illustrated in Figure 60, the ramp is synchronized to the
drainsource ringing. If the ramp exceeds the 2.5 V
threshold while the drainsource voltage is below V
in
, the
ramp is extended until it oscillates above V
in
so that the drive
will turn on at the next valley.
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| NCP1611GEVB | 制造商:ON Semiconductor 功能描述:PG - ACDC CONVERSION - Bulk 制造商:ON Semiconductor 功能描述:EVAL BOARD, NCP1611, POWER FACTOR CORRECTION; Silicon Manufacturer:On Semiconductor; Silicon Core Number:NCP1611; Kit Application Type:Power Management; Application Sub Type:Power Factor Correction (PFC) ;RoHS Compliant: Yes |
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