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參數(shù)資料
| 型號(hào)： | NCP1603D100R2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 28/30頁 |
| 文件大?。?/td> | 302K |
| 描述： | IC CTLR PFC/PWM COMBO 16-SOIC |
| 產(chǎn)品變化通告： | Product Discontinuation 21/Jun/2007 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 模式： | 臨界傳導(dǎo)（CRM），間歇導(dǎo)電（DCM） |
| 頻率 - 開關(guān)： | 58kHz |
| 電流 - 啟動(dòng)： | 17µA |
| 電源電壓： | 9 V ~ 18 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
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NCP1603
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28
In order to prevent wrongly triggering the latch
protection function, it is generaly recommended to put a
pForder decoupling ceramic capacitor across the CS2 pin
to remove possible highfrequency noise there.
To set the V
CC
overvoltage protection, the circuit is
configured in Figure 74. A PNP bipolar transistor is added
to open the Zener diode Z
OVP
when Out2 is high in order
to stop any interference of the normal operation of current
sense. It is because the Zener diode easily pulls high the
CS2 pin voltage to 1.0 V and that interferes with the normal
operation of the current sense when the output is high. The
OVP threshold V
CC2(OVP)
is expressed in Equation 26.
V
CC2(OVP)
+ V
ZOVP
) 3 V
(eq. 26)
Figure 74. V
CC
Latched OVP Application Circuit
CS2
V
CC2
R
CS2
Z
OVP
R
S2
(6) Latched Overvoltage Protection (OVP)
As long as an external protection on CS2 pin (Pin 3) does
not affect the normal regulation operation of current sense,
the protection can be implemented. An alternative is to
implement the output overvoltage protection by an
optocoupler in Figure 75. The leakage current of the added
circuit is up to the zener diode at the output voltage. When
there is no overvoltage, the leakage is small and it does not
affect the normal operation. A resistor paralleled to the
optocoupler is added to share the potential increasing
leakage current of the zener diode due to temperature
variation. The Zener diode at the output voltage is
recommended to be a 1 mA operating current at the
threshold voltage. Then, this current is coupled through the
optocoupler and inserts a similar order of current
(depending on the currenttransferratio CTR of the
optocoupler) into CS2 pin. The CS2 pin is capable of up to
100 mA and with an internal 9 V antiparallel ESD diode
but it is recommended to put a 8.2 V Zener diode there to
further protect the pin.
Figure 75. Output Latched OVP Application Circuit
CS2
V
CC2
R
CS2
Z
OVP
R
S2
V
out
(7) Dual Thermal Shutdown (TSD)
The NCP1603 consists of two individual dies that
incorporates their individual thermal shutdown. The PFC
thermal circuitry disables the PFC gate drive Out1 and then
keeps the power switch off when its junction temperature
exceeds 170 癈 typically. The PFC gate drive Out1 is then
enabled once the temperature drops below typically 125癈
(i.e., 45癈 hysteresis).
The PWM thermal circuitry disables the PWM gate drive
Out2 and then keeps the power switch off when its junction
temperature exceeds 165癈 typically. The PWM gate drive
Out2 is then enabled once the temperature drops below
typically 140癈 and the circuit is unplugged (to make V
CC2
drops below 4.0 V).
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