參數(shù)資料
型號： NCP1603D100R2G
廠商： ON Semiconductor
文件頁數(shù)： 19/30頁
文件大?。?/td> 302K
描述： IC CTLR PFC/PWM COMBO 16-SOIC
產(chǎn)品變化通告： Product Discontinuation 21/Jun/2007
標準包裝： 2,500
模式： 臨界傳導(dǎo)（CRM），間歇導(dǎo)電（DCM）
頻率 - 開關(guān)： 58kHz
電流 - 啟動： 17µA
電源電壓： 9 V ~ 18 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC
包裝： 帶卷 (TR)
NCP1603
http://onsemi.com
19
Frequency Jittering
93.6 kHz
100 kHz
106.4 kHz
5 ms
time
PWM Section Oscillator Frequency
Figure 51. Frequency Jittering of PWM Oscillator
Frequency jittering is a method used to soften the EMI
signature by spreading the energy in the vicinity of the main
switching component. The PWM Section offers a typical
?.4% deviation on the nominal switching frequency
(100 kHz typical). A sweep sawtooth modulates the
100 kHz clock up and down with a 5.0 ms period.
Figure 51 illustrates the ?.4% variation of the jittering
oscillator frequency versus time.
Fault Condition
Figure 52 illustrates the fault detection circuitry and its
timing diagram. When fault (or output short circuit)
happens, the output voltage collapses and the optocoupler
is opened. V
FB2
 is internally pulled to be higher than 3.0 V
(3.8 V typical). Then, the controller activates an error flag
when (V
FB2
/3) is greater than the softstart voltage V
SS
that is 1.0 V after the 2.5 ms from startup.
When the circuit is powering up in the beginning, the
output voltage is not yet established and FB2 pin (Pin 2) is
opened. Therefore, there is a 125 ms timer to allow the
circuit to establish an initial output voltage. Then, a fault
(or short circuit) condition is recognized when an error flag
(V
FB2
  q 3.0 V) can last for 125 ms. When a fault is
detected, Out2 (Pin 13) goes low. The power supply stops
delivering power to the output. On the other hand, the V
aux
(= V
CC1
) also goes low. The V
aux
 will restore immediately
when the error flag disappears.
This fault detection method offers advantage of getting
rid of the auxiliary winding information that cannot truely
represent the output voltage when the flyback transformer
is badly coupled.
-
+
2
FB2
Vdd
20 k
55 k
25 k
V
FB2
V
FB2
3
SoftStart
1 V Max
V
SS
Start Vaux
Enable Vaux/PFC
125 ms
Delay
&
Fault
Disable
Vaux/PFC
and Out2
SoftStart Period 2.5 ms
Figure 52. Block Diagram and Timing Diagram of Fault Detection
1 V
V
FB2
/3
V
SS
V
aux
125ms
V
aux
 starts when V
FB2
 is
within regulation window
(V
FB2
 < 3 V).
(i.e., normal operation)
V
aux
 stops when V
FB2
 is out of
regulation window (V
FB2
 > 3 V)
for more than 125 ms.
(i.e., fault condition)
1 V
time
time
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