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參數(shù)資料
| 型號： | NCP1603D100R2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 20/30頁 |
| 文件大?。?/td> | 302K |
| 描述： | IC CTLR PFC/PWM COMBO 16-SOIC |
| 產(chǎn)品變化通告： | Product Discontinuation 21/Jun/2007 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 模式： | 臨界傳導(dǎo)（CRM），間歇導(dǎo)電（DCM） |
| 頻率 - 開關(guān)： | 58kHz |
| 電流 - 啟動： | 17µA |
| 電源電壓： | 9 V ~ 18 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
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NCP1603
http://onsemi.com
20
5.6 V
12.6 V
7.7 V
0A
V
CC2
I
D
Startup current source
charging the V
CC
capacitor
Startup circuit turns off
when V
CC2
is 12.6 V
Circuit sleeps when
V
CC2
is below 7.7 V
Maximum drain current
is limited to 1 / R
CS2
Startup circuit turns on
when V
CC2
is 5.6 V
Switching starts when
V
CC2
reaches 12.6 V
Peak drain current follows
a 2.5 ms softstart envelope
Switching is missing
in every two V
CC
hiccup cycles
featuring a double hiccup
Figure 53. Timing Diagram of Fault Condition
time
Figure 53 illustrates the timing diagram of V
CC2
and the
secondstage drain current I
D
in fault condition. The V
CC
drops because output voltage collapses. When V
CC
drops
below V
CC(off)
(7.7 V typical), the Drive Output signal
disappears and the V
CC
continues to drop. When bias
voltage V
CC
drops to V
CC(latch)
(5.6 V typical), the startup
current source activates and charge up the V
CC
until V
CC
reaches V
CC(on)
(12.6 V typical). The internal 2.5 ms
softstart activates after V
CC
reaches V
CC(on)
(12.6 V
typical). The peak drain current follows its 2.5 ms
envelope. The power supply dissipates some power due to
the switching signal of Out2 and waits for possible
autorecovery of operation when the fault is cleared.
As shown in Figure 53, NCP1603 has a double hiccup
feature that allows the drain current in every two V
CC
hiccup cycle in fault condition. The double hiccup
feature offers fewer power dissipation during fault
condition comparing to single hiccup .
If the fault is cleared (V
FB2
< 3.0 V
SS
) and V
CC
remains
above V
CC2(off)
(7.7 V typical), the circuit will resume its
operation. Otherwise, the V
CC
will continue this
12.67.75.612.6 V hiccup mode until the fault or bulk
voltage is cleared.
Standby Condition
The output voltage rises up excessively in standby
condition and the V
FB2
drops. A set point of 25% of the
maximum of V
FB2
(i.e., 3.0 V) is defined to be the standby
threshold. Hence, the standby threshold is V
stby
= 25% ?/DIV>
3.0 V = 0.75 V.
FB2
125 ms
delay
&
Leave standby
+
2
0.75 V / 1.25 V
V
FB2
enable Vaux /
Standby
disable
Vaux/
PFC
Section
Figure 54. Block Diagram and Timing Diagram of
Standby Detection
V
FB2
V
aux
1.25 V
0.75 V
125 ms
V
aux
stops when V
FB2
is
below 0.75 V and cannot go
above 1.25 V for 125 ms
V
aux
restores when
V
FB2
goes above 1.25 V
time
time
PFC Section
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