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參數(shù)資料
| 型號： | NCP1603D100R2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 27/30頁 |
| 文件大?。?/td> | 302K |
| 描述： | IC CTLR PFC/PWM COMBO 16-SOIC |
| 產(chǎn)品變化通告： | Product Discontinuation 21/Jun/2007 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 模式： | 臨界傳導(dǎo)（CRM），間歇導(dǎo)電（DCM） |
| 頻率 - 開關(guān)： | 58kHz |
| 電流 - 啟動： | 17µA |
| 電源電壓： | 9 V ~ 18 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
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NCP1603
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27
entering Osc pin and a capacitor is added to remove some
possible noise As a result, the current in Figure 73 may not
necessarily passes through the bulk capacitor for fewer
ripple current there.
Figure 72. Synchronization Configuration
OSC
Out2
Figure 73. Synchronization Timing Diagram
PWM drive
PFC drive
(DCM)
current
Phase 1
current
Phase 2
Output Drive
The output stages of the PFC section and PWM section are
designed for direct drive of power MOSFET. However, it is
recommended to connect a current limiting resistor to the gate
of the power MOSFET. The PFC section output is capable of
up to 500 mA and +750 mA peak drive current and has a
typical rise and fall time of 53 and 32 ns with a 1.0 nF load
while the PWM section output is capable of up to "1.0 A
peak drive current and has a typical rise and fall time of 40 ns
and a fall time of 15 ns with a 1.0 nF capacitive load.
Safety Features of NCP1603
(1) Bulk Voltage Overvoltage Protection (OVP)
When the PFC feedback current I
FB1
is higher than 107%
of the reference current I
ref
(i.e., the bulk voltage V
bulk
is
higher than 107% of its nominal value), the PFC Drive
Output pin (Pin 7) of the device goes low for protection and
the switch of the V
control
processing circuit is kept off. The
circuit automatically resumes operation when the output
voltage is lower than 107%.
The maximum OVP threshold is limited to 225 mA that
corresponds to 225 mA ?1.95 MW + 5.0 V = 443.75 V
when R
FB1
= 1.95 MW (e.g., 910 kW + 910 kW + 130 kW)
and V
FB1
= 5.0 V (for the worst case referring to
Figure 31). Hence, it is generally recommended to use
450 V rating output capacitor to allow some design margin.
(2) Bulk Voltage Undervoltage Protection (UVP)
When the PFC feedback current I
FB1
is smaller than 8%
of the reference current I
ref
, the PFC section is shutdown
and consumes less than 50 mA. In normal situation of the
boost converter configuration, the output bulk voltage
V
bulk
is always higher than input voltage V
in
and the I
FB1
is higher than 8% of the reference current. It enables the
PFC section to operate. Hence, UVP happens when the
bulk voltage V
bulk
is abnormally undervoltage, the FB1
pin (Pin 9) is opened, or the FB1 pin (Pin 9) is manually
pulled low.
(3) PFCStage Overcurrent Protection
When the PFC sense current I
S1
is higher than typically
200 mA, the PFC Drive Output (Pin 7) goes low. It
represents the PFCstage inductor current i
L
exceeds a
userdefined value. The operation automatically resumes
when the inductor current becomes lower than this
userdefined value at the next clock cycle.
(4) PWMStage ShortCircuit Protection
When V
FB2
remains higher than 3.0 V for 125 ms, a fault
is recognized. The PFCstage (i.e., V
aux
) will be disabled
and the V
CC2
will operate a double hiccup shown in
Figure 53. The operation will be selfrecovered if V
CC2
is
above 7.7 V and V
FB2
is below 3.0 V. This fault protection
is implemented by a timer and independent of badly
coupled auxiliary transformer winding.
(5) Latched V
CC
Overvoltage Protection
The normal operating voltage range of the CS2 pin
(Pin 3) is between 0 V and I
limit
(1.0 V typical). When the
voltage is above 1.0 V, the Out2 (Pin 13) goes low. When
the voltage increases above 3.0 V, the Out2 goes low and
stays latched off until the circuit is reset by unplugging
from main supply to make V
CC2
drop below V
CC(reset)
(4.0 V typical). This feature also offers the designer the
flexibility to implement an externally pullhigh latched
protection or latched shutdown circuit.
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