參數(shù)資料
型號(hào)： NCP1603D100R2G
廠商： ON Semiconductor
文件頁數(shù)： 23/30頁
文件大小： 302K
描述： IC CTLR PFC/PWM COMBO 16-SOIC
產(chǎn)品變化通告： Product Discontinuation 21/Jun/2007
標(biāo)準(zhǔn)包裝： 2,500
模式： 臨界傳導(dǎo)（CRM），間歇導(dǎo)電（DCM）
頻率 - 開關(guān)： 58kHz
電流 - 啟動(dòng)： 17µA
電源電壓： 9 V ~ 18 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC
包裝： 帶卷 (TR)
NCP1603
http://onsemi.com
23
a 9.0 V ESD zener diode. The 3.9 V maximum limit of this
V
ton
 indirectly limits the maximum on time.
The V
control
  processing circuit generates V
ton
  from
control voltage V
control
  and time information of zero
inductor   current. The circuit in Figure 61   makes
Equations 9 and 10 where the value of resistor R
1
 is much
higher than the value of resistor R
2
 (R
1
 >> R
2
).
Figure 61. V
control
 Processing Circuit
+

closed when zero current
10
C
control
V
control
R
1
R
2
R
3
C
1
C
3
V
ton
V
ton
+
T V
control
t
1
) t
2
for DCM
(eq. 9)
V
ton
+ V
control
for CRM
(eq. 10)
It is noted that V
ton
 is always greater than or equal to
V
control
 (V
ton
 q V
control
).
In summary, the input impedance Z
in
 in Equation 11 is
obtained from Equations 3 through 10.
Z
in
+
V
in
I
in
+
2LI
ch
C
ramp
V
control
(eq. 11)
Control voltage V
control
  comes from the PFC boost
circuit output voltage (i.e., bulk voltage V
bulk
) that is a
slowly varying signal. The bandwidth of V
control
 can be
additionally limited by inserting an external capacitor
C
control
  to the V
control
  pin (Pin 10) in Figure 62. The
internal 300 kW resistor and the capacitor C
control
 create a
lowpass filter that has a bandwidth f
control
 in Equation 12.
It is generally recommended to limit the bandwidth below
20 Hz to achieve power factor correction. Typical value of
C
control
 is 0.1 mF.
C
control
u
1
2p300kW f
control
(eq. 12)
Figure 62. V
control
 LowPass Filtering
300k
Regulation Block
10
C
control
V
control
V
reg
I
ref
I
ref
96%
I
FB1
V
control
Processing
Circuit
If the bandwidth of V
control
 is much less than the 50 or
60 Hz line frequency, the input impedance Z
in
 is slowly
varying or roughly constant. Then, the power factor
correction is achieved in DCM and CRM.
Maximum Power in PFC Section
Input and output power (P
in
 and P
out
) are derived in
Equations 13 and 14 when the circuit efficiency ? is
obtained or assumed. The variable V
ac
 stands for the RMS
input voltage.
P
in
+
V
ac
2
Z
in
+
V
ac
2
C
ramp
V
control
2LI
ch
(eq. 13)
P
out
+ h P
in
+
hV
ac
2
C
ramp
V
control
2LI
ch
(eq. 14)
From Equations 13 and 14, control voltage V
control
controls the amount of output power, input power, or input
impedance. The maximum value of the control voltage
V
control
 is 1.05 V (i.e., V
control(max)
 = 1.05 V). A parameter
called maximum power resistor R
power
 (10.5 kW typical) is
defined in Equation 18 and restricted to have a maximum
?0% variation (i.e., 9.5 kW p R
power
 p 11.5 kW) for
defining the maximum power in an application.
R
power
+
V
control(max)
I
ch
+
1.05 V
100 mA
+ 10.5 kW
(eq. 15)
It means that the maximum input and output power
(P
in(max)
 and P
out(max)
) are limited to ?0% variation.
P
in(max)
+
V
ac
2
C
ramp
R
power
2 L
(eq. 16)
P
out(max)
+
hV
ac
2
C
ramp
R
power
2 L
(eq. 17)
The maximum input current I
ac(max)
  to deliver the
maximum input power P
in(max)
 is also derived in (eq.14).
The suffix ac stands for RMS value.
I
ac(max)
+
P
in(max)
V
ac
+
V
acC
ramp
R
power
2 L
(eq. 18)
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