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參數(shù)資料
| 型號(hào)： | NCP1603D100R2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 18/30頁 |
| 文件大小： | 302K |
| 描述： | IC CTLR PFC/PWM COMBO 16-SOIC |
| 產(chǎn)品變化通告： | Product Discontinuation 21/Jun/2007 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 模式： | 臨界傳導(dǎo)（CRM），間歇導(dǎo)電（DCM） |
| 頻率 - 開關(guān)： | 58kHz |
| 電流 - 啟動(dòng)： | 17µA |
| 電源電壓： | 9 V ~ 18 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
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NCP1603
http://onsemi.com
18
The UVLO start thresholds of V
CC1
is V
CC1(on)
(10.5 V
typical) and the maximum allowable limit is 18 V. On the
other hand, the V
aux
is enabled when V
CC2
is over V
CC2(off)
(7.7 V typical). Hence, there are two possible operating
regions in Figure 49. In the nonusable region the V
aux
is
not high enough to turn on the PFC section. Therefore, the
flyback transformer auxiliary winding must be between
V
CC1(on)
(10.5 V typical) and 18 V.
Regulation in the PWM Section
The PWM section (or the second stage) of the NCP1603
is NCP1230 that is a currentmode fixedfrequency PWM
flyback controller with internal compensation ramp. The
simplified block diagram of the duty cycle regulation
section is in Figure 50. A 100 kHz clock oscillator is
modulated by adding a frequency jittering feature. This
modulated 100 kHz clock signal turns the Out2 (pin 13)
high in each switching cycle. The Out2 goes low when the
currentloop feedback signal intersects with the output
voltageloop feedback signal. A duty cycle is therefore
generated. The maximum duty ratio is limited to D
max
(80% typical).
V
out
2
Opto
Coupler
FB2
Vdd
20 k
55 k
25 k
V
FB2
V
FB2
3
SoftStart
Processing
Circuit
-
+
200 ns
LEB
SoftStart Period 2.5 ms
V
FB2
3
1 V Max
PWM
R
S
Q
Max Duty
= 80%
V
CC2
13
3
Out2
V
bulk
Flyback
Drain
Current
I
D
CS2
R
S2
R
CS2
6.4% Frequency
Jittering
Modulation
100 kHz
Oscillator
2.3 V
0 V
100 kHz
Jittering Ramp
18 k
Figure 50. Block Diagram of Duty Cycle Regulation in the PWM Section
The currentloop feedback circuit consists of a typical
200 ns Leading Edge Blanking (LEB) that is to prevent a
premature reset of the output due to noise, a pair of sense
resistors R
CS2
and R
S2
that sense the flyback drain current
I
D
, and a 0to2.3 V jittering ramp that adds a ramp
compensation for a stability improvement to the
currentmode control possibly in continuous mode
operation.
The V
FB2
is approximately divided by 3 by an internal
pair of resistors (55 kW and 25 kW). The softstart
processing circuit reduces the initial voltageloop
feedback signal (V
FB2
/ 3) for 2.5 ms. After this 2.5 ms, the
softstart disappears. As a result, the startup envelope of
the peak drain current (or duty ratio) ramps up gradually for
2.5 ms. It is noted that the 2.5 ms is counted when the PWM
die circuit is reset that is when V
CC2
reaches V
CC2(on)
(12.6 V typical). This softstart feature offers a reduced
transient voltage and current stress on the power circuit
during the startup.
Excessive output voltage causes more the optocoupler
current. It pulls down the V
FB2
through FB2 pin (Pin 2) and
generates a lower duty ratio. The output voltage reduces.
Insufficient output voltage reduces the optocoupler
current. If the current is too small, the V
FB2
is eventually
pulled high than 3.0 V (3.8 V typical). The (V
FB2
/3) signal
is then clamped to an internal 1.0 V limit. If the ramp is
ignored (i.e., R
S2
= 0), the maximum possible drain current
is derived as:
I
D(max)
+
1 V
R
CS2
(eq. 2)
It is noted that resistor R
S2
will affect the percentage of
the ramp getting compared for the modulation. Hence, a
large value of the R
S2
increase the ramp and will reduce the
possible maximum duty ratio.
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