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參數(shù)資料
| 型號： | NAND512W4B2BN6T |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 32M X 16 FLASH 3V PROM, 25000 ns, PDSO48 |
| 封裝： | 12 X 20 MM, PLASTIC, TSOP-48 |
| 文件頁數(shù)： | 10/58頁 |
| 文件大?。?/td> | 943K |
| 代理商： | NAND512W4B2BN6T |
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NAND512-B, NAND01G-B, NAND02G-B, NAND04G-B, NAND08G-B
18/58
COMMAND SET
All bus write operations to the device are interpret-
ed by the Command Interface. The Commands
are input on I/O0-I/O7 and are latched on the rising
edge of Write Enable when the Command Latch
Enable signal is high. Device operations are se-
lected by writing specific commands to the Com-
mand
Register.
The
two-step
command
sequences for program and erase operations are
imposed to maximize data security.
The
Commands
are
summarized
in
Table 10. Commands
Note: 1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown.
2. For consecutive Read operations the 00h command does not need to be repeated.
3. Only during Cache Read busy.
Command
Bus Write Operations(1)
Commands
accepted
during busy
1st CYCLE
2nd CYCLE
3rd CYCLE
4th CYCLE
Read
00h(2)
30h
–
Random Data Output
05h
E0h
–
Cache Read
00h
31h
–
Exit Cache Read
34h
–
Yes(3)
Page Program
(Sequential Input default)
80h
10h
–
Random Data Input
85h
–
Copy Back Program
00h
35h
85h
10h
Cache Program
80h
15h
–
Block Erase
60h
D0h
–
Reset
FFh
–
Yes
Read Electronic Signature
90h
–
Read Status Register
70h
–
Yes
Read Block Lock Status
7Ah
–
Blocks Unlock
23h
24h
–
Blocks Lock
2Ah
–
Blocks Lock-Down
2Ch
–
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