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參數(shù)資料
| 型號： | NAND512R4A2CZD6E |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 32M X 16 FLASH 1.8V PROM, 15000 ns, PBGA55 |
| 封裝： | 8 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-55 |
| 文件頁數(shù)： | 7/55頁 |
| 文件大?。?/td> | 1377K |
| 代理商： | NAND512R4A2CZD6E |
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NAND512-A2C
Signal descriptions
3.6
Read Enable (R)
The Read Enable, R, controls the sequential data output during read operations. Data is
valid tRLQV after the falling edge of R. The falling edge of R also increments the internal
column address counter by one.
3.7
Write Enable (W)
The Write Enable input, W, controls writing to the command interface, input address and
data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10 s (min) is required before the
command interface is ready to accept a command. It is recommended to keep Write Enable
High during the recovery time.
3.8
Write Protect (WP)
The Write Protect pin is an input that gives a hardware protection against unwanted program
or erase operations. When Write Protect is Low, VIL, the device does not accept any
program or erase operations.
It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down.
3.9
Ready/Busy (RB)
The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R
controller is currently active.
When Ready/Busy is Low, VOL, a read, program or erase operation is in progress. When the
operation completes Ready/Busy goes High, VOH.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
During power-up and power-down a recovery time of 10 s (min) is required before the
command interface is ready to accept a command. During the recovery time the RB signal is
Low, VOL.
Refer to the Section 10.1: Ready/Busy signal electrical characteristics for details on how to
calculate the value of the pull-up resistor.
3.10
VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main
power supply for all operations (read, program and erase).
An internal voltage detector disables all functions whenever VDD is below the VLKO threshold
(see Figure 36: Data protection) to protect the device from any involuntary program/erase
operations during power-transitions.
Each device in a system should have VDD decoupled with a 0.1 F capacitor. The PCB track
widths should be sufficient to carry the required program and erase currents
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