參數(shù)資料
型號: NAND128W4A3AN6E
廠商: STMICROELECTRONICS
元件分類: PROM
英文描述: 8M X 16 FLASH 3V PROM, 10000 ns, PDSO48
封裝: 12 X 20 MM, LEAD FREE, PLASTIC, TSOP-48
文件頁數(shù): 51/56頁
文件大?。?/td> 882K
代理商: NAND128W4A3AN6E
55/56
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
RELATED DOCUMENTATION
STMicroelectronics has published a set of application notes to support the NAND Flash memories. They
are available from the ST Website
www.st.com. or from your local ST Distributor.
REVISION HISTORY
Table 29. Document Revision History
Date
Version
Revision Details
06-Jun-2003
1.0
First Issue
07-Aug-2003
2.0
Design Phase
27-Oct-2003
3.0
Engineering Phase
03-Dec-2003
4.0
Document promoted from Target Specification to Preliminary Data status.
VCC changed to VDD and ICC to IDD.
Title of Table 2.. changed to “Product Description” and Page Program Typical Timing
for NANDXXXR3A devices corrected. Table 1., Product List, inserted on page 2.
13-Apr-2004
5.0
WSOP48 and VFBGA55 packages added, VFBGA63 (9 x 11 x 1mm) removed.
Figure 19., Cache Program Operation, modified and note 2 modified. Note removed
Meaning of tBLBH4 modified, partly replaced by tWHBH1 and tWHRL min for 3V devices
References removed from RELATED DOCUMENTATION section and reference
made to ST Website instead.
Note 3 to Table 7., Address Insertion, x16 Devices removed. Only 00h Pointer
operations are valid before a Cache Program operation. IDD4 removed from Table
Waveform. Small text changes.
28-May-2004
6.0
TFBGA55 package added (mechanical data to be announced). 512Mb Dual Die
devices added. Figure 19., Cache Program Operation modified.
Package code changed for TFBGA63 8.5 x 15 x 1.2mm, 6x8 ball array, 0.8mm pitch
(1Gbit Dual Die devices) in Table 28., Ordering Information Scheme.
02-Jul-2004
7.0
Cache Program removed from document. TFBGA55 package specifications added
Test
conditions
modified
for
VOL and VOH parameters in Table 19., DC
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