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參數(shù)資料
| 型號： | NAND02GW4B2CZA1E |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 128M X 16 FLASH 3V PROM, 25000 ns, PBGA63 |
| 封裝： | 9.50 X 12 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-63 |
| 文件頁數(shù)： | 7/60頁 |
| 文件大?。?/td> | 1335K |
| 代理商： | NAND02GW4B2CZA1E |
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NAND01G-B2B, NAND02G-B2C
Signals description
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3.7
Write Enable (W)
The Write Enable input, W, controls writing to the command interface, input address and
data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10 s (min) is required before the
command interface is ready to accept a command. It is recommended to keep Write Enable
High during the recovery time.
3.8
Write Protect (WP)
The Write Protect pin is an input that gives a hardware protection against unwanted program
or erase operations. When Write Protect is Low, VIL, the device does not accept any
program or erase operations.
It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down.
3.9
Ready/Busy (RB)
The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R
controller is currently active. When Ready/Busy is Low, VOL, a read, program or erase
operation is in progress. When the operation completes Ready/Busy goes High, VOH.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
Refer to the Section 11.1: Ready/Busy signal electrical characteristics for details on how to
calculate the value of the pull-up resistor.
During power-up and power-down a minimum recovery time of 10 s is required before the
command interface is ready to accept a command. During this period the RB signal is Low,
VOL.
3.10
VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main
power supply for all operations (read, program and erase).
An internal voltage detector disables all functions whenever VDD is below VLKO (see
power-transitions.
Each device in a system should have VDD decoupled with a 0.1 F capacitor. The PCB track
widths should be sufficient to carry the required program and erase currents.
3.11
VSS ground
Ground, VSS, is the reference for the power supply. It must be connected to the system
ground.
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