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參數(shù)資料
| 型號： | NAND02GW4B2CZA1E |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 128M X 16 FLASH 3V PROM, 25000 ns, PBGA63 |
| 封裝： | 9.50 X 12 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-63 |
| 文件頁數(shù)： | 40/60頁 |
| 文件大?。?/td> | 1335K |
| 代理商： | NAND02GW4B2CZA1E |
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NAND01G-B2B, NAND02G-B2C
DC and AC parameters
45/60
Table 25.
AC characteristics for operations(1)
Symbol
Alt.
symbol
Parameter
1.8 V
devices
3 V
devices
Unit
tALLRL1
tAR
Address Latch Low to
Read Enable Low
Read electronic signature
Min
10
ns
tALLRL2
Read cycle
Min
10
ns
tBHRL
tRR
Ready/Busy High to Read Enable Low
Min
20
ns
tBLBH1
Ready/Busy Low to
Ready/Busy High
Read busy time
Max
25
s
tBLBH2
tPROG
Program busy time
Max
700
s
tBLBH3
tBERS
Erase busy time
Max
3
ms
tBLBH4
tRST
Reset busy time, during ready
Max
5
s
Reset busy time, during read
Max
5
s
Reset busy time, during program
Max
10
s
Reset busy time, during erase
Max
500
s
tBLBH5
tCBSY
Cache busy time
Typ
3
s
Max
700
s
tCLLRL
tCLR
Command Latch Low to Read Enable Low
Min
10
ns
tDZRL
tIR
Data Hi-Z to Read Enable Low
Min
0
ns
tEHQZ
tCHZ
Chip Enable High to Output Hi-Z
Max
30
ns
tRHQZ
tRHZ
Read Enable High to Output Hi-z
Max
30
ns
tWHWH
tADL
(2)
Last address latched to data loading time during program
operations
Min
100
ns
tVHWH
tVLWH
tWW
(3)
Write protection time
Min
100
ns
tELQV
tCEA
Chip Enable Low to Output Valid
Max
45
25
ns
tRHRL
tREH
Read Enable High to
Read Enable Low
Read Enable High hold time
Min
15
10
ns
tEHQX
TOH
Chip Enable High or Read Enable high to Output Hold
Min
10
ns
tRHQX
tRLRH
tRP
Read Enable Low to
Read Enable High
Read Enable pulse width
Min
25
15
ns
tRLRL
tRC
Read Enable Low to
Read Enable Low
Read cycle time
Min
50
30
ns
tRLQV
tREA
Read Enable Low to
Output Valid
Read Enable access time
Max
30
20
ns
Read ES access time(4)
tWHBH
tR
Write Enable High to
Ready/Busy High
Read busy time
Max
25
s
tWHBL
tWB
Write Enable High to Ready/Busy Low
Max
100
ns
tWHRL
tWHR
Write Enable High to Read Enable Low
Min
60
ns
1.
The time to ready depends on the value of the pull-up resistor tied to the ready/busy pin. See Figure 31, Figure 32 and
2.
tWHWH is the time from W rising edge during the final address cycle to W rising edge during the first data cycle.
3.
During a program/erase enable operation, tWW is the delay from WP high to W High.
During a program/erase disable Operation, tWW is the delay from WP Low to W High.
4.
ES = electronic signature.
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