參數(shù)資料
型號(hào)： NAND02GW4B2CZA1E
廠商： NUMONYX
元件分類： PROM
英文描述： 128M X 16 FLASH 3V PROM, 25000 ns, PBGA63
封裝： 9.50 X 12 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-63
文件頁數(shù)： 16/60頁
文件大小： 1335K
代理商： NAND02GW4B2CZA1E
NAND01G-B2B, NAND02G-B2C
Device operations
23/60
6.2
Cache read
The cache read operation is used to improve the read throughput by reading data using the
cache register. As soon as the user starts to read one page, the device automatically loads
the next page into the cache register.
A cache read operation consists of three steps (see Table 10: Commands):
1.
One bus cycle is required to setup the Cache Read command (the same as the
standard Read command)
2.
Four or five (refer to Table 6 and Table 7) bus cycles are then required to input the start
address
3.
One bus cycle is required to issue the Cache Read Confirm command to start the
P/E/R controller.
The start address must be at the beginning of a page (column address = 00h, see Table 8
and Table 9). This allows the data to be output uninterrupted after the latency time (tBLBH1),
The Ready/Busy signal can be used to monitor the start of the operation. During the latency
period the Ready/Busy signal goes Low, after this the Ready/Busy signal goes High, even if
the device is internally downloading page n+1.
Once the cache read operation has started, the status register can be read using the Read
Status Register command.
During the operation, SR5 can be read, to find out whether the internal reading is ongoing
(SR5 = ‘0’), or has completed (SR5 = ‘1’), while SR6 indicates whether the cache register is
ready to download new data.
To exit the cache read operation an Exit Cache Read command must be issued (see
If the Exit Cache Read command is issued while the device is internally reading page n+1,
pages n and n+1 will not be output.
Figure 8.
Cache read operation
I/O
RB
Address
inputs
ai13104b
00h
Read
Setup
code
31h
Cache
Read
Confirm
code
Busy
tBLBH1
(Read Busy time)
1st page
Data output
2nd page
3rd page
last page
34h
Exit
Cache
Read
code
Block N
tBLBH4
R
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