- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299551 > NAND02GW4B2CZA1E (NUMONYX) 128M X 16 FLASH 3V PROM, 25000 ns, PBGA63 PDF資料下載
參數(shù)資料
| 型號： | NAND02GW4B2CZA1E |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 128M X 16 FLASH 3V PROM, 25000 ns, PBGA63 |
| 封裝： | 9.50 X 12 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-63 |
| 文件頁數(shù)： | 6/60頁 |
| 文件大?。?/td> | 1335K |
| 代理商： | NAND02GW4B2CZA1E |
第1頁第2頁第3頁第4頁第5頁當(dāng)前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
Signals description
NAND01G-B2B, NAND02G-B2C
3
Signals description
See Figure 2: Logic diagram, and Table 3: Signal names, for a brief overview of the signals
connected to this device.
3.1
Inputs/outputs (I/O0-I/O7)
Input/outputs 0 to 7 are used to input the selected address, output the data during a read
operation or input a command or data during a write operation. The inputs are latched on
the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or
the outputs are disabled.
3.2
Inputs/outputs (I/O8-I/O15)
Input/outputs 8 to 15 are only available in x16 devices. They are used to output the data
during a read operation or input data during a write operation. Command and address
Inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.
3.3
Address Latch Enable (AL)
The Address Latch Enable activates the latching of the address inputs in the command
interface. When AL is High, the inputs are latched on the rising edge of Write Enable.
3.4
Command Latch Enable (CL)
The Command Latch Enable activates the latching of the command inputs in the command
interface. When CL is High, the inputs are latched on the rising edge of Write Enable.
3.5
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is Low, VIL, the device is selected. If Chip Enable goes
High, vIH, while the device is busy, the device remains selected and does not go into standby
mode.
3.6
Read Enable (R)
The Read Enable pin, R, controls the sequential data output during read operations. Data is
valid tRLQV after the falling edge of R. The falling edge of R also increments the internal
column address counter by one.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NAND16GW3B4DN6E | 4G X 4 FLASH 3V PROM, 25 ns, PDSO48 |
| NAND512R4A2CZD6E | 32M X 16 FLASH 1.8V PROM, 15000 ns, PBGA55 |
| NB2762ASNR2G | HF - EMI REDUCER; Package: TSOP-6; No of Pins: 6; Container: Tape and Reel; Qty per Container: 2500 |
| NB2762ASNR2 | EMI REDUCER SERIES; Package: TSOP-6; No of Pins: 6; Container: Tape and Reel; Qty per Container: 2500 |
| NC7SB121P5X | 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO5 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NAND04GR3B2DDI6 | 制造商:Micron Technology Inc 功能描述:NAND - Gel-pak, waffle pack, wafer, diced wafer on film |
| NAND04GR3B2DN6E | 功能描述:IC FLASH 4GBIT 48TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:576 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040 |
| NAND04GR3B2DZL6F | 制造商:Micron Technology Inc 功能描述:NAND - Tape and Reel |
| NAND04GR3B2EN6E | 制造商:Micron Technology Inc 功能描述:NAND - Trays |
| NAND04GR3B2EN6F | 制造商:Micron Technology Inc 功能描述:NAND - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。