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參數(shù)資料
| 型號： | MX98728 |
| 英文描述： | GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION |
| 中文描述： | GMAC的單芯片10/100快速以太網(wǎng)控制器的一般應用程序 |
| 文件頁數(shù)： | 44/71頁 |
| 文件大小： | 389K |
| 代理商： | MX98728 |
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44
P/N:PM0723
REV. 1.0, JUL. 13, 2000
MX98728EC
5.1 Host Accesses to the Packet Memory
Host Burst Read
Receive packet is removed by host through a high speed
burst read buffer which is 32 bits x 4 or 16 bits x 4 de-
pending on H16_32 pin. The Burst Read buffer can be
accessed by two methods : DACKB and DREQB based
protocol or IO based access ( RRD port ) to registers
located at 43h-40h. Before any packet buffer read can
be issued, the RX buffer must be initialized with proper
page pointers set up at appropriate locations. Any read
access to the Burst Read buffer, using DACKB/DREQB
protocol or through IO register 43h-40h, will get data from
the current location within the receive buffer ring pointed
to by the RRP page pointer and the RRPBC byte counter.
When the RRPBC reaches the boundary of a page, it
will increment the RRP page pointer by 1 and reset
RRPBC itself automatically. Of course, the software can
always overwrite the RRP pointer. This write will also
reset the RRPBC counter.
A burst read access can be issued only when either the
DREQB pin is asserted low or the register 3A.2 bit (
DREQB status bit ) is low which indicates 4 consecu-
tive data transfers are ready inside the GMAC's Burst
Read Buffer for a burst read transfer. The host can read
the RRD data port or issue DACKB in any length less
than or equal to 4 reads. When the host have finished
reading the entire packet and there might be junk data in
the Burst Read Buffer, the host can issue a RRP page
pointer update (e.g. RRP+1), which will automatically
reset the Burst Read Buffer and the related control cir-
cuit. After the RRP page pointer update, the Burst Read
buffer will fetch 4 consecutive double word from the new
page if there are more data available.
Note : The current read physical location in the packet
memory = the RRP pointer ( mapped to MA[19:8] ) cas-
caded with the RRPBC byte counter ( mapped to MA[7:0]
).
Host Write
The TWD data port ( offset 37H - 34H ) is used for write
accesses to the transmit buffer ring. The current write
position within the transmit buffer ring is pointed to by
the TWP page pointer and the TWPBC byte counter. Since
a write access to the transmit buffer ring involves the
packet memory arbitration, the SRDY pin or the register
3A.0 ( WRDYB ) bit can be used for the wait state pur-
pose. For system that supports the SRDY pin for wait
states, a write to the TWD port can be issued at any
time. This write will be treated as the top priority in the
packet memory's arbitration. If no SRDY pin is supported
in the system, inquire the register 3A.0 bit ( WRDYB ) for
0 to see if a new write can be issued. Otherwise, if WRDYB
is 1 which means the previous write to TWD is still pend-
ing inside GMAC, a new write must not be issued. When
the TWPBC counter reaches the boundary of a page, it
will increment the TWP page pointer and reset the
TWPBC byte counter automatically. Of course, software
can always overwrite the TWP pointer which also reset
the internal TWPBC byte counter.
Note : The current write physical location in the packet
memory = the TWP pointer ( mapped to MA[19:8] ) cas-
caded with the TWPBC byte counter ( mapped to MA[7:0]
).
A write cycle is completed by the assertion of the SRDY
signal high to indicate that GMAC has secured the write
data. Or reading the register 3A.0 bit ( WRDYB ) for 0
which indicates that the previous write was done and a
new write can be issued to GMAC. No burst is supported
for any write access. A write access is independent of
the status of the DREQB pin or the DREQB register bit.
Due to the arbitration for the packet memory access, a
write cycle ( without first reading a 0 from the WRDYB
bit ) may encounter some "Wait state" which delays the
assertion of SRDY for certain time. In any case, Bus
Integrity Check Timer ( BICT ) can be pre-programmed
to "terminate" any write cycle that runs over BICT time-
out period. Such a time-out can both generate an inter-
rupt to the software and flash LED0 and LED1 at identi-
cal low visible frequency to resolve a potential bus hang,
bus dead lock problem.
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